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https://issues.apache.org/jira/browse/CASSANDRA-7438?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel&focusedCommentId=14225531#comment-14225531
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Robert Stupp commented on CASSANDRA-7438:
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bq. alignment requirements for 4 or 8 byte CAS
Intel P6: must be 8-byte aligned (if cross cache line) or unaligned (if in same
cache line) - but: _However, it is recommend that locked accesses be aligned on
their natural boundaries for better system performance_
(https://stackoverflow.com/questions/1415256/alignment-requirements-for-atomic-x86-instructions).
Side note: heh - there's even support for 128bit atomic operations (cmpxchg16b)
- but where's the primitive for that in Java... :(
> Serializing Row cache alternative (Fully off heap)
> --------------------------------------------------
>
> Key: CASSANDRA-7438
> URL: https://issues.apache.org/jira/browse/CASSANDRA-7438
> Project: Cassandra
> Issue Type: Improvement
> Components: Core
> Environment: Linux
> Reporter: Vijay
> Assignee: Vijay
> Labels: performance
> Fix For: 3.0
>
> Attachments: 0001-CASSANDRA-7438.patch
>
>
> Currently SerializingCache is partially off heap, keys are still stored in
> JVM heap as BB,
> * There is a higher GC costs for a reasonably big cache.
> * Some users have used the row cache efficiently in production for better
> results, but this requires careful tunning.
> * Overhead in Memory for the cache entries are relatively high.
> So the proposal for this ticket is to move the LRU cache logic completely off
> heap and use JNI to interact with cache. We might want to ensure that the new
> implementation match the existing API's (ICache), and the implementation
> needs to have safe memory access, low overhead in memory and less memcpy's
> (As much as possible).
> We might also want to make this cache configurable.
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