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utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git


The following commit(s) were added to refs/heads/master by this push:
     new 1df69ab  Fix nucleo-f413zh BSP
1df69ab is described below

commit 1df69abda19e01457c69303a7dd0ba52065c1fc1
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Tue Jun 12 13:50:56 2018 -0700

    Fix nucleo-f413zh BSP
    
    This fixes BSP "partition" sizes, linker scripts and adds correct startup
    file for stm32f413.
---
 hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld         |   6 +-
 hw/bsp/nucleo-f413zh/bsp.yml                       |  20 +-
 hw/bsp/nucleo-f413zh/nucleo-f413zh.ld              |   4 +-
 .../src/arch/cortex_m4/startup_STM32F40x.s         | 353 ------------
 .../src/arch/cortex_m4/startup_stm32f413xx.s       | 597 +++++++++++++++++++++
 hw/mcu/stm/stm32f4xx/stm32f413.ld                  | 213 ++++++++
 6 files changed, 825 insertions(+), 368 deletions(-)

diff --git a/hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld 
b/hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld
index 54a0c8d..59e0f3a 100644
--- a/hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld
+++ b/hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld
@@ -20,9 +20,9 @@
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
-  CCM (rwx) : ORIGIN = 0x20040000, LENGTH = 64K
-  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+  CCM (rwx) :  ORIGIN = 0x20040000, LENGTH = 64K
+  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 256K
 }
 
 /* The bootloader does not contain an image header */
diff --git a/hw/bsp/nucleo-f413zh/bsp.yml b/hw/bsp/nucleo-f413zh/bsp.yml
index ac7ec13..a47c933 100644
--- a/hw/bsp/nucleo-f413zh/bsp.yml
+++ b/hw/bsp/nucleo-f413zh/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
 bsp.compiler: compiler/arm-none-eabi-m4
 bsp.linkerscript:
     - "hw/bsp/nucleo-f413zh/nucleo-f413zh.ld"
-    - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+    - "hw/mcu/stm/stm32f4xx/stm32f413.ld"
 bsp.linkerscript.BOOT_LOADER.OVERWRITE:
     - "hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld"
-    - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+    - "hw/mcu/stm/stm32f4xx/stm32f413.ld"
 bsp.downloadscript: "hw/bsp/nucleo-f413zh/nucleo-f413zh_download.sh"
 bsp.debugscript: "hw/bsp/nucleo-f413zh/nucleo-f413zh_debug.sh"
 bsp.downloadscript.WINDOWS.OVERWRITE: 
"hw/bsp/nucleo-f413zh/nucleo-f413zh_download.cmd"
@@ -36,28 +36,28 @@ bsp.flash_map:
         FLASH_AREA_BOOTLOADER:
             device: 0
             offset: 0x08000000
-            size: 16kB
+            size: 32kB
         FLASH_AREA_IMAGE_0:
             device: 0
             offset: 0x08020000
-            size: 384kB
+            size: 640kB
         FLASH_AREA_IMAGE_1:
             device: 0
-            offset: 0x08080000
-            size: 384kB
+            offset: 0x080C0000
+            size: 640kB
         FLASH_AREA_IMAGE_SCRATCH:
             device: 0
-            offset: 0x080e0000
+            offset: 0x08160000
             size: 128kB
 
         # User areas.
         FLASH_AREA_REBOOT_LOG:
             user_id: 0
             device: 0
-            offset: 0x08004000
+            offset: 0x08008000
             size: 16kB
         FLASH_AREA_NFFS:
             user_id: 1
             device: 0
-            offset: 0x08008000
-            size: 32kB
+            offset: 0x0800C000
+            size: 80kB
diff --git a/hw/bsp/nucleo-f413zh/nucleo-f413zh.ld 
b/hw/bsp/nucleo-f413zh/nucleo-f413zh.ld
index af6266d..32333fe 100644
--- a/hw/bsp/nucleo-f413zh/nucleo-f413zh.ld
+++ b/hw/bsp/nucleo-f413zh/nucleo-f413zh.ld
@@ -17,12 +17,12 @@
  * under the License.
  */
 
-/* Linker script for STM32F407 when running from flash and using the 
bootloader */
+/* Linker script for STM32F413 when running from flash and using the 
bootloader */
 
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx) :  ORIGIN = 0x08020000, LENGTH = 384K /* First image slot. */
+  FLASH (rx) :  ORIGIN = 0x08020000, LENGTH = 640K /* First image slot. */
   CCM (rwx) :   ORIGIN = 0x20040000, LENGTH = 64K
   RAM (rwx) :   ORIGIN = 0x20000000, LENGTH = 256K
 }
diff --git a/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_STM32F40x.s 
b/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_STM32F40x.s
deleted file mode 100644
index e84feac..0000000
--- a/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_STM32F40x.s
+++ /dev/null
@@ -1,353 +0,0 @@
-/* File: startup_STM32F40x.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- *   GCC for ARM Embedded Processors
- * Version: V1.4
- * Date: 09 July 2012
- *
- * Copyright (c) 2011, 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-    .syntax unified
-    .arch armv7-m
-
-    .section .stack
-    .align 3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xc00
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
-__StackTop:
-    .size __StackTop, . - __StackTop
-
-    .section .heap
-    .align 3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
-
-    .section .isr_vector
-    .align 2
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-    /* External interrupts */
-    .long     WWDG_IRQHandler               /* Window WatchDog */
-    .long     PVD_IRQHandler                /* PVD through EXTI Line detection 
*/
-    .long     TAMP_STAMP_IRQHandler         /* Tamper and TimeStamps through 
the EXTI line */
-    .long     RTC_WKUP_IRQHandler           /* RTC Wakeup through the EXTI 
line */
-    .long     FLASH_IRQHandler              /* FLASH */
-    .long     RCC_IRQHandler                /* RCC */
-    .long     EXTI0_IRQHandler              /* EXTI Line0 */
-    .long     EXTI1_IRQHandler              /* EXTI Line1 */
-    .long     EXTI2_IRQHandler              /* EXTI Line2 */
-    .long     EXTI3_IRQHandler              /* EXTI Line3 */
-    .long     EXTI4_IRQHandler              /* EXTI Line4 */
-    .long     DMA1_Stream0_IRQHandler       /* DMA1 Stream 0 */
-    .long     DMA1_Stream1_IRQHandler       /* DMA1 Stream 1 */
-    .long     DMA1_Stream2_IRQHandler       /* DMA1 Stream 2 */
-    .long     DMA1_Stream3_IRQHandler       /* DMA1 Stream 3 */
-    .long     DMA1_Stream4_IRQHandler       /* DMA1 Stream 4 */
-    .long     DMA1_Stream5_IRQHandler       /* DMA1 Stream 5 */
-    .long     DMA1_Stream6_IRQHandler       /* DMA1 Stream 6 */
-    .long     ADC_IRQHandler                /* ADC1, ADC2 and ADC3s */
-    .long     CAN1_TX_IRQHandler            /* CAN1 TX */
-    .long     CAN1_RX0_IRQHandler           /* CAN1 RX0 */
-    .long     CAN1_RX1_IRQHandler           /* CAN1 RX1 */
-    .long     CAN1_SCE_IRQHandler           /* CAN1 SCE */
-    .long     EXTI9_5_IRQHandler            /* External Line[9:5]s */
-    .long     TIM1_BRK_TIM9_IRQHandler      /* TIM1 Break and TIM9 */
-    .long     TIM1_UP_TIM10_IRQHandler      /* TIM1 Update and TIM10 */
-    .long     TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation 
and TIM11 */
-    .long     TIM1_CC_IRQHandler            /* TIM1 Capture Compare */
-    .long     TIM2_IRQHandler               /* TIM2 */
-    .long     TIM3_IRQHandler               /* TIM3 */
-    .long     TIM4_IRQHandler               /* TIM4 */
-    .long     I2C1_EV_IRQHandler            /* I2C1 Event */
-    .long     I2C1_ER_IRQHandler            /* I2C1 Error */
-    .long     I2C2_EV_IRQHandler            /* I2C2 Event */
-    .long     I2C2_ER_IRQHandler            /* I2C2 Error */
-    .long     SPI1_IRQHandler               /* SPI1 */
-    .long     SPI2_IRQHandler               /* SPI2 */
-    .long     USART1_IRQHandler             /* USART1 */
-    .long     USART2_IRQHandler             /* USART2 */
-    .long     USART3_IRQHandler             /* USART3 */
-    .long     EXTI15_10_IRQHandler          /* External Line[15:10]s */
-    .long     RTC_Alarm_IRQHandler          /* RTC Alarm (A and B) through 
EXTI Line */
-    .long     OTG_FS_WKUP_IRQHandler        /* USB OTG FS Wakeup through EXTI 
line */
-    .long     TIM8_BRK_TIM12_IRQHandler     /* TIM8 Break and TIM12 */
-    .long     TIM8_UP_TIM13_IRQHandler      /* TIM8 Update and TIM13 */
-    .long     TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation 
and TIM14 */
-    .long     TIM8_CC_IRQHandler            /* TIM8 Capture Compare */
-    .long     DMA1_Stream7_IRQHandler       /* DMA1 Stream7 */
-    .long     FSMC_IRQHandler               /* FSMC */
-    .long     SDIO_IRQHandler               /* SDIO */
-    .long     TIM5_IRQHandler               /* TIM5 */
-    .long     SPI3_IRQHandler               /* SPI3 */
-    .long     UART4_IRQHandler              /* UART4 */
-    .long     UART5_IRQHandler              /* UART5 */
-    .long     TIM6_DAC_IRQHandler           /* TIM6 and DAC1&2 underrun errors 
*/
-    .long     TIM7_IRQHandler               /* TIM7 */
-    .long     DMA2_Stream0_IRQHandler       /* DMA2 Stream 0 */
-    .long     DMA2_Stream1_IRQHandler       /* DMA2 Stream 1 */
-    .long     DMA2_Stream2_IRQHandler       /* DMA2 Stream 2 */
-    .long     DMA2_Stream3_IRQHandler       /* DMA2 Stream 3 */
-    .long     DMA2_Stream4_IRQHandler       /* DMA2 Stream 4 */
-    .long     ETH_IRQHandler                /* Ethernet */
-    .long     ETH_WKUP_IRQHandler           /* Ethernet Wakeup through EXTI 
line */
-    .long     CAN2_TX_IRQHandler            /* CAN2 TX */
-    .long     CAN2_RX0_IRQHandler           /* CAN2 RX0 */
-    .long     CAN2_RX1_IRQHandler           /* CAN2 RX1 */
-    .long     CAN2_SCE_IRQHandler           /* CAN2 SCE */
-    .long     OTG_FS_IRQHandler             /* USB OTG FS */
-    .long     DMA2_Stream5_IRQHandler       /* DMA2 Stream 5 */
-    .long     DMA2_Stream6_IRQHandler       /* DMA2 Stream 6 */
-    .long     DMA2_Stream7_IRQHandler       /* DMA2 Stream 7 */
-    .long     USART6_IRQHandler             /* USART6 */
-    .long     I2C3_EV_IRQHandler            /* I2C3 event */
-    .long     I2C3_ER_IRQHandler            /* I2C3 error */
-    .long     OTG_HS_EP1_OUT_IRQHandler     /* USB OTG HS End Point 1 Out */
-    .long     OTG_HS_EP1_IN_IRQHandler      /* USB OTG HS End Point 1 In */
-    .long     OTG_HS_WKUP_IRQHandler        /* USB OTG HS Wakeup through EXTI 
*/
-    .long     OTG_HS_IRQHandler             /* USB OTG HS */
-    .long     DCMI_IRQHandler               /* DCMI */
-    .long     CRYP_IRQHandler               /* CRYP crypto */
-    .long     HASH_RNG_IRQHandler           /* Hash and Rng */
-    .long     FPU_IRQHandler                /* FPU */
-
-    .size    __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
-Reset_Handler:
-/* Copy data core section from flash to RAM */
-    ldr    r1, =__etext
-    ldr    r2, =__coredata_start__
-    ldr    r3, =__coredata_end__
-
-.LC0:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt    .LC0
-
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy 
from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
-    ldr    r1, =__ecoredata
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-.LC1:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt    .LC1
-
-/* Set the bss core section to zero */
-    mov     r0, #0
-    ldr     r1, =__corebss_start__
-    ldr     r2, =__corebss_end__
-
-.LC2:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt    .LC2
-
-    /* Set the other bss section to zero as well*/
-    ldr     r1, =__bss_start__
-    ldr     r2, =__bss_end__
-
-.LC3:
-    cmp     r1, r2
-    itt     lt
-    strlt   r0, [r1], #4
-    blt    .LC3
-
-/* Call system initialization and startup routines */
-    ldr    r0, =SystemInit
-    blx    r0
-    ldr    r0, =_start
-    bx     r0
-    .pool
-    .size Reset_Handler, . - Reset_Handler
-
-    .text
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_default_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name :
-    b    .
-    .size    \handler_name, . - \handler_name
-    .endm
-
-    def_default_handler    NMI_Handler
-    def_default_handler    HardFault_Handler
-    def_default_handler    MemManage_Handler
-    def_default_handler    BusFault_Handler
-    def_default_handler    UsageFault_Handler
-    def_default_handler    SVC_Handler
-    def_default_handler    DebugMon_Handler
-    def_default_handler    PendSV_Handler
-    def_default_handler    SysTick_Handler
-    def_default_handler    Default_Handler
-
-    .macro    def_irq_default_handler    handler_name
-    .weak     \handler_name
-    .set      \handler_name, Default_Handler
-    .endm
-
-    def_irq_default_handler     WWDG_IRQHandler
-    def_irq_default_handler     PVD_IRQHandler
-    def_irq_default_handler     TAMP_STAMP_IRQHandler
-    def_irq_default_handler     RTC_WKUP_IRQHandler
-    def_irq_default_handler     FLASH_IRQHandler
-    def_irq_default_handler     RCC_IRQHandler
-    def_irq_default_handler     EXTI0_IRQHandler
-    def_irq_default_handler     EXTI1_IRQHandler
-    def_irq_default_handler     EXTI2_IRQHandler
-    def_irq_default_handler     EXTI3_IRQHandler
-    def_irq_default_handler     EXTI4_IRQHandler
-    def_irq_default_handler     DMA1_Stream0_IRQHandler
-    def_irq_default_handler     DMA1_Stream1_IRQHandler
-    def_irq_default_handler     DMA1_Stream2_IRQHandler
-    def_irq_default_handler     DMA1_Stream3_IRQHandler
-    def_irq_default_handler     DMA1_Stream4_IRQHandler
-    def_irq_default_handler     DMA1_Stream5_IRQHandler
-    def_irq_default_handler     DMA1_Stream6_IRQHandler
-    def_irq_default_handler     ADC_IRQHandler
-    def_irq_default_handler     CAN1_TX_IRQHandler
-    def_irq_default_handler     CAN1_RX0_IRQHandler
-    def_irq_default_handler     CAN1_RX1_IRQHandler
-    def_irq_default_handler     CAN1_SCE_IRQHandler
-    def_irq_default_handler     EXTI9_5_IRQHandler
-    def_irq_default_handler     TIM1_BRK_TIM9_IRQHandler
-    def_irq_default_handler     TIM1_UP_TIM10_IRQHandler
-    def_irq_default_handler     TIM1_TRG_COM_TIM11_IRQHandler
-    def_irq_default_handler     TIM1_CC_IRQHandler
-    def_irq_default_handler     TIM2_IRQHandler
-    def_irq_default_handler     TIM3_IRQHandler
-    def_irq_default_handler     TIM4_IRQHandler
-    def_irq_default_handler     I2C1_EV_IRQHandler
-    def_irq_default_handler     I2C1_ER_IRQHandler
-    def_irq_default_handler     I2C2_EV_IRQHandler
-    def_irq_default_handler     I2C2_ER_IRQHandler
-    def_irq_default_handler     SPI1_IRQHandler
-    def_irq_default_handler     SPI2_IRQHandler
-    def_irq_default_handler     USART1_IRQHandler
-    def_irq_default_handler     USART2_IRQHandler
-    def_irq_default_handler     USART3_IRQHandler
-    def_irq_default_handler     EXTI15_10_IRQHandler
-    def_irq_default_handler     RTC_Alarm_IRQHandler
-    def_irq_default_handler     OTG_FS_WKUP_IRQHandler
-    def_irq_default_handler     TIM8_BRK_TIM12_IRQHandler
-    def_irq_default_handler     TIM8_UP_TIM13_IRQHandler
-    def_irq_default_handler     TIM8_TRG_COM_TIM14_IRQHandler
-    def_irq_default_handler     TIM8_CC_IRQHandler
-    def_irq_default_handler     DMA1_Stream7_IRQHandler
-    def_irq_default_handler     FSMC_IRQHandler
-    def_irq_default_handler     SDIO_IRQHandler
-    def_irq_default_handler     TIM5_IRQHandler
-    def_irq_default_handler     SPI3_IRQHandler
-    def_irq_default_handler     UART4_IRQHandler
-    def_irq_default_handler     UART5_IRQHandler
-    def_irq_default_handler     TIM6_DAC_IRQHandler
-    def_irq_default_handler     TIM7_IRQHandler
-    def_irq_default_handler     DMA2_Stream0_IRQHandler
-    def_irq_default_handler     DMA2_Stream1_IRQHandler
-    def_irq_default_handler     DMA2_Stream2_IRQHandler
-    def_irq_default_handler     DMA2_Stream3_IRQHandler
-    def_irq_default_handler     DMA2_Stream4_IRQHandler
-    def_irq_default_handler     ETH_IRQHandler
-    def_irq_default_handler     ETH_WKUP_IRQHandler
-    def_irq_default_handler     CAN2_TX_IRQHandler
-    def_irq_default_handler     CAN2_RX0_IRQHandler
-    def_irq_default_handler     CAN2_RX1_IRQHandler
-    def_irq_default_handler     CAN2_SCE_IRQHandler
-    def_irq_default_handler     OTG_FS_IRQHandler
-    def_irq_default_handler     DMA2_Stream5_IRQHandler
-    def_irq_default_handler     DMA2_Stream6_IRQHandler
-    def_irq_default_handler     DMA2_Stream7_IRQHandler
-    def_irq_default_handler     USART6_IRQHandler
-    def_irq_default_handler     I2C3_EV_IRQHandler
-    def_irq_default_handler     I2C3_ER_IRQHandler
-    def_irq_default_handler     OTG_HS_EP1_OUT_IRQHandler
-    def_irq_default_handler     OTG_HS_EP1_IN_IRQHandler
-    def_irq_default_handler     OTG_HS_WKUP_IRQHandler
-    def_irq_default_handler     OTG_HS_IRQHandler
-    def_irq_default_handler     DCMI_IRQHandler
-    def_irq_default_handler     CRYP_IRQHandler
-    def_irq_default_handler     HASH_RNG_IRQHandler
-    def_irq_default_handler     FPU_IRQHandler
-    def_irq_default_handler     DEF_IRQHandler
-
-    .end
diff --git a/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_stm32f413xx.s 
b/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_stm32f413xx.s
new file mode 100644
index 0000000..ca70bd1
--- /dev/null
+++ b/hw/bsp/nucleo-f413zh/src/arch/cortex_m4/startup_stm32f413xx.s
@@ -0,0 +1,597 @@
+/**
+  
******************************************************************************
+  * @file      startup_stm32f413xx.s
+  * @author    MCD Application Team
+  * @brief     STM32F413xx Devices vector table for GCC based toolchains.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR 
address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  
******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without 
modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright 
notice,
+  *      this list of conditions and the following disclaimer in the 
documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its 
contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 
USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  
******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack       /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/*
+ * mynewt specific corebss clearing.
+ */
+  ldr   r2, =__corebss_start__
+  b     LoopFillZeroCoreBss
+
+/* Zero fill the bss segment. */
+FillZeroCoreBss:
+  movs  r3, #0
+  str   r3, [r2], #4
+
+LoopFillZeroCoreBss:
+  ldr   r3, =__corebss_end__
+  cmp   r2, r3
+  bcc   FillZeroCoreBss
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+/* Call the libc entry point.*/
+  bl  _start
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, 
preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+  .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+  .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .globl __isr_vector
+__isr_vector:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog               
              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line 
detection             */
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through 
the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI 
line            */
+  .word     FLASH_IRQHandler                  /* FLASH                         
              */
+  .word     RCC_IRQHandler                    /* RCC                           
              */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                    
              */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                    
              */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                    
              */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                    
              */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                    
              */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                 
              */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                 
              */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                 
              */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                 
              */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                 
              */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                 
              */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                 
              */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s          
              */
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                       
              */
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                      
              */
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                      
              */
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                      
              */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s           
              */
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9           
              */
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10         
              */
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation 
and TIM11      */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare          
              */
+  .word     TIM2_IRQHandler                   /* TIM2                          
              */
+  .word     TIM3_IRQHandler                   /* TIM3                          
              */
+  .word     TIM4_IRQHandler                   /* TIM4                          
              */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                    
              */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                    
              */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                    
              */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                    
              */
+  .word     SPI1_IRQHandler                   /* SPI1                          
              */
+  .word     SPI2_IRQHandler                   /* SPI2                          
              */
+  .word     USART1_IRQHandler                 /* USART1                        
              */
+  .word     USART2_IRQHandler                 /* USART2                        
              */
+  .word     USART3_IRQHandler                 /* USART3                        
              */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s         
              */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through 
EXTI Line       */
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through 
EXTI line         */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12          
              */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13         
              */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation 
and TIM14      */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare          
              */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                  
              */
+  .word     FSMC_IRQHandler                   /* FSMC                          
              */
+  .word     SDIO_IRQHandler                   /* SDIO                          
              */
+  .word     TIM5_IRQHandler                   /* TIM5                          
              */
+  .word     SPI3_IRQHandler                   /* SPI3                          
              */
+  .word     UART4_IRQHandler                  /* UART4                         
              */
+  .word     UART5_IRQHandler                  /* UART5                         
              */
+  .word     TIM6_DAC_IRQHandler               /* TIM6, DAC1 and DAC2           
              */
+  .word     TIM7_IRQHandler                   /* TIM7                          
              */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                 
              */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                 
              */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                 
              */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                 
              */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                 
              */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM1 Filter0                
              */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM1 Filter1                
              */
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                       
              */
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                      
              */
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                      
              */
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                      
              */
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                    
              */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                 
              */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                 
              */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                 
              */
+  .word     USART6_IRQHandler                 /* USART6                        
              */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                    
              */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                    
              */
+  .word     CAN3_TX_IRQHandler                /* CAN3 TX                       
              */
+  .word     CAN3_RX0_IRQHandler               /* CAN3 RX0                      
              */
+  .word     CAN3_RX1_IRQHandler               /* CAN3 RX1                      
              */
+  .word     CAN3_SCE_IRQHandler               /* CAN3 SCE                      
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     RNG_IRQHandler                    /* RNG                           
              */
+  .word     FPU_IRQHandler                    /* FPU                           
              */
+  .word     UART7_IRQHandler                  /* UART7                         
              */
+  .word     UART8_IRQHandler                  /* UART8                         
              */
+  .word     SPI4_IRQHandler                   /* SPI4                          
              */
+  .word     SPI5_IRQHandler                   /* SPI5                          
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     SAI1_IRQHandler                   /* SAI1                          
              */
+  .word     UART9_IRQHandler                  /* UART9                         
              */
+  .word     UART10_IRQHandler                 /* UART10                        
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     QUADSPI_IRQHandler                /* QuadSPI                       
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     0                                 /* Reserved                      
              */
+  .word     FMPI2C1_EV_IRQHandler             /* FMPI2C1 Event                 
              */
+  .word     FMPI2C1_ER_IRQHandler             /* FMPI2C1 Error                 
              */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                        
              */
+  .word     DFSDM2_FLT0_IRQHandler            /* DFSDM2 Filter0                
              */
+  .word     DFSDM2_FLT1_IRQHandler            /* DFSDM2 Filter1                
              */
+  .word     DFSDM2_FLT2_IRQHandler            /* DFSDM2 Filter2                
              */
+  .word     DFSDM2_FLT3_IRQHandler            /* DFSDM2 Filter3                
              */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMP_STAMP_IRQHandler
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      CAN1_TX_IRQHandler
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX0_IRQHandler
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_TIM9_IRQHandler
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_TIM10_IRQHandler
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      OTG_FS_WKUP_IRQHandler
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FSMC_IRQHandler
+   .thumb_set FSMC_IRQHandler,Default_Handler
+
+   .weak      SDIO_IRQHandler
+   .thumb_set SDIO_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      OTG_FS_IRQHandler
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      CAN3_TX_IRQHandler
+   .thumb_set CAN3_TX_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX0_IRQHandler
+   .thumb_set CAN3_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN3_RX1_IRQHandler
+   .thumb_set CAN3_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN3_SCE_IRQHandler
+   .thumb_set CAN3_SCE_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler
+   .thumb_set RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      UART10_IRQHandler
+   .thumb_set UART10_IRQHandler,Default_Handler
+
+   .weak      QUADSPI_IRQHandler
+   .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+    .weak     FMPI2C1_EV_IRQHandler
+   .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
+
+   .weak      FMPI2C1_ER_IRQHandler
+   .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_FLT0_IRQHandler
+   .thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_FLT1_IRQHandler
+   .thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_FLT2_IRQHandler
+   .thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_FLT3_IRQHandler
+   .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF 
FILE****/
diff --git a/hw/mcu/stm/stm32f4xx/stm32f413.ld 
b/hw/mcu/stm/stm32f4xx/stm32f413.ld
new file mode 100644
index 0000000..e9bf1b3
--- /dev/null
+++ b/hw/mcu/stm/stm32f4xx/stm32f413.ld
@@ -0,0 +1,213 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __coredata_start__
+ *   __coredata_end__
+ *   __corebss_start__
+ *   __corebss_end__
+ *   __ecoredata
+ *   __ecorebss
+ */
+ENTRY(Reset_Handler)
+
+_estack = 0x20050000;
+
+SECTIONS
+{
+    /* Reserve space at the start of the image for the header. */
+    .imghdr (NOLOAD):
+    {
+        . = . + _imghdr_size;
+    } > FLASH
+
+    .text :
+    {
+        __isr_vector_start = .;
+        KEEP(*(.isr_vector))
+        __isr_vector_end = .;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+
+    __exidx_end = .;
+
+    __etext = .;
+
+    .vector_relocation :
+    {
+        . = ALIGN(4);
+        __vector_tbl_reloc__ = .;
+        . = . + (__isr_vector_end - __isr_vector_start);
+        . = ALIGN(4);
+    } > RAM
+
+    .coredata :
+    {
+        __coredata_start__ = .;
+        *(.data.core)
+        . = ALIGN(4);
+        __coredata_end__ = .;
+    } > CCM AT > FLASH
+
+    __ecoredata = __etext + SIZEOF(.coredata);
+
+    _sidata = LOADADDR(.data);
+
+    .data :
+    {
+        . = ALIGN(4);
+        _sdata = .;
+        __data_start__ = _sdata;
+        *(vtable)
+        *(.data*)
+
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        _edata = .;
+        __data_end__ = _edata;
+
+    } > RAM AT > FLASH
+
+    .corebss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __corebss_start__ = .;
+        *(.bss.core)
+        . = ALIGN(4);
+        __corebss_end__ = .;
+        *(.corebss*)
+        *(.bss.core.nz)
+        . = ALIGN(4);
+        __ecorebss = .;
+    } > CCM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+    } > RAM
+
+    . = ALIGN(8);
+    __HeapBase = .;
+    __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);
+
+    _ram_start = ORIGIN(RAM);
+    _ccram_start = ORIGIN(CCM);
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > CCM
+
+    /* Set stack top to end of CCM; stack limit is bottom of stack */
+    __StackTop = ORIGIN(CCM) + LENGTH(CCM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check for CCM overflow */
+    ASSERT(__StackLimit >= __ecorebss, "CCM overflow!")
+}
+

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