This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 1b0dc396d87d390e82b7d22b330141bc86783b7a
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Wed May 6 08:35:10 2020 +0200
stm32l4xx: Fix clock discrepancies
syscfg default value for MSI clock was using constant
suitable for calibration filed resulting in default
MSI clock speed 100kHz.
AHB, APB1, APB2 dividers descriptions mentioned 64MHz
max frequencies while this MCU has 80MHz limit.
---
hw/mcu/stm/stm32l4xx/syscfg.yml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mcu/stm/stm32l4xx/syscfg.yml b/hw/mcu/stm/stm32l4xx/syscfg.yml
index eb778c6..8a92651 100644
--- a/hw/mcu/stm/stm32l4xx/syscfg.yml
+++ b/hw/mcu/stm/stm32l4xx/syscfg.yml
@@ -53,7 +53,7 @@ syscfg.defs:
STM32_CLOCK_MSI_CLOCK_RANGE:
description: MSI clock range
- value: 'RCC_MSICALIBRATION_DEFAULT'
+ value: 'RCC_MSIRANGE_8'
STM32_CLOCK_HSE:
description: Enable high-speed external clock source
@@ -96,15 +96,15 @@ syscfg.defs:
value: 0
STM32_CLOCK_AHB_DIVIDER:
- description: AHB CLK1 prescaler (64MHz max)
+ description: AHB CLK1 prescaler (80MHz max)
value: 0
STM32_CLOCK_APB1_DIVIDER:
- description: APB low-speed prescaler (64MHz max)
+ description: APB low-speed prescaler (80MHz max)
value: 0
STM32_CLOCK_APB2_DIVIDER:
- description: APB high-speed prescaler (64MHz max)
+ description: APB high-speed prescaler (80MHz max)
value: 0
STM32_FLASH_LATENCY:
