apache-mynewt-bot removed a comment on pull request #2348: URL: https://github.com/apache/mynewt-core/pull/2348#issuecomment-670647756
<!-- style-bot --> ## Style check summary ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md) #### hw/bus/drivers/i2c_nrf91_twim/src/i2c_nrf91_twim.c <details> ```diff @@ -40,17 +40,17 @@ #if MYNEWT_VAL(I2C_NRF91_TWIM_STAT) STATS_SECT_START(twim_stats_section) - STATS_SECT_ENTRY(sda_lo_err) /* SDA pulled low on r/w */ - STATS_SECT_ENTRY(sda_lo_err_nrecov) /* SDA pulled low on r/w (not recovered)*/ - STATS_SECT_ENTRY(scl_hi_err) /* SCL unresponsive */ - STATS_SECT_ENTRY(scl_hi_err_nrecov) /* SCL unresponsive (not recovered)*/ +STATS_SECT_ENTRY(sda_lo_err) /* SDA pulled low on r/w */ +STATS_SECT_ENTRY(sda_lo_err_nrecov) /* SDA pulled low on r/w (not recovered)*/ +STATS_SECT_ENTRY(scl_hi_err) /* SCL unresponsive */ +STATS_SECT_ENTRY(scl_hi_err_nrecov) /* SCL unresponsive (not recovered)*/ STATS_SECT_END STATS_NAME_START(twim_stats_section) - STATS_NAME(twim_stats_section, sda_lo_err) - STATS_NAME(twim_stats_section, sda_lo_err_nrecov) - STATS_NAME(twim_stats_section, scl_hi_err) - STATS_NAME(twim_stats_section, scl_hi_err_nrecov) +STATS_NAME(twim_stats_section, sda_lo_err) +STATS_NAME(twim_stats_section, sda_lo_err_nrecov) +STATS_NAME(twim_stats_section, scl_hi_err) +STATS_NAME(twim_stats_section, scl_hi_err_nrecov) STATS_NAME_END(twim_stats_section) #endif @@ -352,7 +352,8 @@ nrf_twim->TASKS_STOP = 1; nrf_twim->ENABLE = TWIM_ENABLE_ENABLE_Disabled; nrf_twim->ENABLE = TWIM_ENABLE_ENABLE_Enabled; - }; + } + ; #if MYNEWT_VAL(I2C_NRF91_TWIM_STAT) STATS_INC(dd->stats, scl_hi_err_nrecov); ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_flash.c <details> ```diff @@ -25,7 +25,7 @@ #include "nrfx_config_nrf9160.h" #include "nrf_nvmc.h" -#define NRF91K_FLASH_SECTOR_SZ 4096 +#define NRF91K_FLASH_SECTOR_SZ 4096 static int nrf91k_flash_read(const struct hal_flash *dev, uint32_t address, void *dst, uint32_t num_bytes); @@ -49,8 +49,8 @@ const struct hal_flash nrf91k_flash_dev = { .hf_itf = &nrf91k_flash_funcs, .hf_base_addr = 0x00000000, - .hf_size = 1024 * 1024, /* XXX read from factory info? */ - .hf_sector_cnt = 256, /* XXX read from factory info? */ + .hf_size = 1024 * 1024, /* XXX read from factory info? */ + .hf_sector_cnt = 256, /* XXX read from factory info? */ .hf_align = 1, .hf_erased_val = 0xff, }; ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_gpio.c <details> ```diff @@ -116,7 +116,7 @@ port->OUTCLR = HAL_GPIO_MASK(pin); } port->PIN_CNF[pin_index] = GPIO_PIN_CNF_DIR_Output | - (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); + (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); port->DIRSET = HAL_GPIO_MASK(pin); return 0; ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_i2c.c <details> ```diff @@ -38,18 +38,18 @@ #define NRF91_SCL_PIN_CONF \ ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \ - (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | \ - (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | \ + (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | \ + (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | \ (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ - (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)) + (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)) #define NRF91_SDA_PIN_CONF NRF91_SCL_PIN_CONF #define NRF91_SCL_PIN_CONF_CLR \ - ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \ - (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | \ - (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | \ - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)) + ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | \ + (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | \ + (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | \ + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ + (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)) #define NRF91_SDA_PIN_CONF_CLR NRF91_SCL_PIN_CONF_CLR struct nrf91_hal_i2c { @@ -83,7 +83,7 @@ static void hal_i2c_delay_us(uint32_t number_of_us) { - register uint32_t delay __ASM ("r0") = number_of_us; + register uint32_t delay __ASM("r0") = number_of_us; __ASM volatile ( #ifdef NRF51 ".syntax unified\n" ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_nvreg.c <details> ```diff @@ -36,7 +36,7 @@ void hal_nvreg_write(unsigned int reg, uint32_t val) { - if(reg < HAL_NVREG_MAX) { + if (reg < HAL_NVREG_MAX) { *regs[reg] = val; } } @@ -46,7 +46,7 @@ { uint32_t val = 0; - if(reg < HAL_NVREG_MAX) { + if (reg < HAL_NVREG_MAX) { val = *regs[reg]; } ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_qspi.c <details> ```diff @@ -98,7 +98,8 @@ static int nrf91k_qspi_read(const struct hal_flash *dev, uint32_t address, - void *dst, uint32_t num_bytes) { + void *dst, uint32_t num_bytes) +{ uint32_t ram_buffer[4]; uint8_t *ram_ptr = NULL; uint32_t read_bytes; @@ -162,7 +163,7 @@ while (num_bytes != 0) { page_limit = (address & ~(MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 1)) + - MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE); + MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE); /* * Use RAM buffer if src or address is not 4 bytes aligned, * or number of bytes to write is less then 4 ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_spi.c <details> ```diff @@ -85,19 +85,19 @@ /* Callback and arguments */ hal_spi_txrx_cb txrx_cb_func; - void *txrx_cb_arg; + void *txrx_cb_arg; }; #if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) struct nrf91_hal_spi nrf91_hal_spi0; #endif -#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) struct nrf91_hal_spi nrf91_hal_spi1; #endif -#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) struct nrf91_hal_spi nrf91_hal_spi2; #endif -#if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) +#if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) struct nrf91_hal_spi nrf91_hal_spi3; #endif @@ -107,17 +107,17 @@ #else NULL, #endif -#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) &nrf91_hal_spi1, #else NULL, #endif -#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) &nrf91_hal_spi2, #else NULL, #endif -#if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) +#if MYNEWT_VAL(SPI_3_MASTER) || MYNEWT_VAL(SPI_3_SLAVE) &nrf91_hal_spi3, #else NULL, @@ -181,7 +181,7 @@ } #endif -#if (MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ +#if (MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_1_SLAVE) || \ MYNEWT_VAL(SPI_2_SLAVE) || MYNEWT_VAL(SPI_3_SLAVE)) static void nrf91_irqs_handler(struct nrf91_hal_spi *spi) @@ -349,34 +349,34 @@ /* Only 8-bit word sizes supported. */ rc = 0; switch (settings->word_size) { - case HAL_SPI_WORD_SIZE_8BIT: - break; - default: - rc = EINVAL; - break; + case HAL_SPI_WORD_SIZE_8BIT: + break; + default: + rc = EINVAL; + break; } switch (settings->data_mode) { - case HAL_SPI_MODE0: - nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE1: - nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE2: - nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE3: - nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | - (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); - break; - default: - nrf_config = 0; - rc = EINVAL; - break; + case HAL_SPI_MODE0: + nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE1: + nrf_config = (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE2: + nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE3: + nrf_config = (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + default: + nrf_config = 0; + rc = EINVAL; + break; } /* NOTE: msb first is 0 so no check done */ @@ -386,31 +386,31 @@ spim->CONFIG = nrf_config; switch (settings->baudrate) { - case 125: - frequency = SPIM_FREQUENCY_FREQUENCY_K125; - break; - case 250: - frequency = SPIM_FREQUENCY_FREQUENCY_K250; - break; - case 500: - frequency = SPIM_FREQUENCY_FREQUENCY_K500; - break; - case 1000: - frequency = SPIM_FREQUENCY_FREQUENCY_M1; - break; - case 2000: - frequency = SPIM_FREQUENCY_FREQUENCY_M2; - break; - case 4000: - frequency = SPIM_FREQUENCY_FREQUENCY_M4; - break; - case 8000: - frequency = SPIM_FREQUENCY_FREQUENCY_M8; - break; - default: - frequency = 0; - rc = EINVAL; - break; + case 125: + frequency = SPIM_FREQUENCY_FREQUENCY_K125; + break; + case 250: + frequency = SPIM_FREQUENCY_FREQUENCY_K250; + break; + case 500: + frequency = SPIM_FREQUENCY_FREQUENCY_K500; + break; + case 1000: + frequency = SPIM_FREQUENCY_FREQUENCY_M1; + break; + case 2000: + frequency = SPIM_FREQUENCY_FREQUENCY_M2; + break; + case 4000: + frequency = SPIM_FREQUENCY_FREQUENCY_M4; + break; + case 8000: + frequency = SPIM_FREQUENCY_FREQUENCY_M8; + break; + default: + frequency = 0; + rc = EINVAL; + break; } spim->FREQUENCY = frequency; @@ -429,26 +429,26 @@ rc = 0; switch (settings->data_mode) { - case HAL_SPI_MODE0: - nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE1: - nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE2: - nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); - break; - case HAL_SPI_MODE3: - nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | - (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); - break; - default: - nrf_config = 0; - rc = EINVAL; - break; + case HAL_SPI_MODE0: + nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE1: + nrf_config = (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE2: + nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + case HAL_SPI_MODE3: + nrf_config = (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + default: + nrf_config = 0; + rc = EINVAL; + break; } if (settings->data_order == HAL_SPI_LSB_FIRST) { @@ -458,11 +458,11 @@ /* Only 8-bit word sizes supported. */ switch (settings->word_size) { - case HAL_SPI_WORD_SIZE_8BIT: - break; - default: - rc = EINVAL; - break; + case HAL_SPI_WORD_SIZE_8BIT: + break; + default: + rc = EINVAL; + break; } return rc; @@ -914,7 +914,7 @@ goto err; } - if (spi->spi_type == HAL_SPI_TYPE_MASTER) { + if (spi->spi_type == HAL_SPI_TYPE_MASTER) { /* Must have a txbuf for master! */ if (txbuf == NULL) { goto err; @@ -1008,7 +1008,7 @@ struct nrf91_hal_spi *spi; NRF91_HAL_SPI_RESOLVE(spi_num, spi); - if (spi->spi_type == HAL_SPI_TYPE_SLAVE) { + if (spi->spi_type == HAL_SPI_TYPE_SLAVE) { spis = spi->nhs_spi.spis; spis->DEF = (uint8_t)val; spis->ORC = (uint8_t)val; ``` </details> #### hw/mcu/nordic/nrf91xxx/src/hal_uart.c <details> ```diff @@ -30,19 +30,19 @@ #define UARTE_INT_ENDTX UARTE_INTEN_ENDTX_Msk -#define UARTE_INT_ENDRX UARTE_INTEN_ENDRX_Msk +#define UARTE_INT_ENDRX UARTE_INTEN_ENDRX_Msk #define UARTE_CONFIG_PARITY UARTE_CONFIG_PARITY_Msk #define UARTE_CONFIG_HWFC UARTE_CONFIG_HWFC_Msk -#define UARTE_ENABLE UARTE_ENABLE_ENABLE_Enabled +#define UARTE_ENABLE UARTE_ENABLE_ENABLE_Enabled #define UARTE_DISABLE UARTE_ENABLE_ENABLE_Disabled /* * Only one UART on NRF 52832. */ struct hal_uart { - uint8_t u_open:1; - uint8_t u_rx_stall:1; - uint8_t u_tx_started:1; + uint8_t u_open : 1; + uint8_t u_rx_stall : 1; + uint8_t u_tx_started : 1; uint8_t u_rx_buf; uint8_t u_tx_buf[8]; hal_uart_rx_char u_rx_func; ``` </details> #### hw/mcu/nordic/nrf91xxx/src/system_nrf9160.c <details> ```diff @@ -1,26 +1,26 @@ /* -Copyright (c) 2009-2018 ARM Limited. All rights reserved. + Copyright (c) 2009-2018 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at + Licensed under the Apache License, Version 2.0 (the License); you may + not use this file except in compliance with the License. + You may obtain a copy of the License at www.apache.org/licenses/LICENSE-2.0 -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an AS IS BASIS, WITHOUT + WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + NOTICE: This file has been modified by Nordic Semiconductor ASA. + + */ + +/* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ #include <stdint.h> @@ -36,206 +36,210 @@ #define __SYSTEM_CLOCK (64000000UL) /*!< nRF9160 Application core uses a fixed System Clock Frequency of 64MHz */ -#define TRACE_PIN_CNF_VALUE ( (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ - (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \ - (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) ) +#define TRACE_PIN_CNF_VALUE ((GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) | \ + (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | \ + (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | \ + (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | \ + (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)) #define TRACE_TRACECLK_PIN (21) #define TRACE_TRACEDATA0_PIN (22) #define TRACE_TRACEDATA1_PIN (23) #define TRACE_TRACEDATA2_PIN (24) #define TRACE_TRACEDATA3_PIN (25) -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#if defined (__CC_ARM) +uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#elif defined (__ICCARM__) +__root uint32_t SystemCoreClock = __SYSTEM_CLOCK; +#elif defined (__GNUC__) +uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; #endif /* Global values used used in Secure mode SystemInit. */ #if !defined(NRF_TRUSTZONE_NONSECURE) - /* Global values used by UICR erase fix algorithm. */ - static uint32_t uicr_erased_value; - static uint32_t uicr_new_value; +/* Global values used by UICR erase fix algorithm. */ +static uint32_t uicr_erased_value; +static uint32_t uicr_new_value; #endif /* Errata are only handled in secure mode since they usually need access to FICR. */ #if !defined(NRF_TRUSTZONE_NONSECURE) - static bool uicr_HFXOSRC_erased(void); - static bool uicr_HFXOCNT_erased(void); -#endif - -void SystemCoreClockUpdate(void) +static bool uicr_HFXOSRC_erased(void); +static bool uicr_HFXOCNT_erased(void); +#endif + +void +SystemCoreClockUpdate(void) { SystemCoreClock = __SYSTEM_CLOCK; } -void SystemInit(void) -{ - //spm_config(); +void +SystemInit(void) +{ + /*spm_config(); */ #if !defined(NRF_TRUSTZONE_NONSECURE) - /* Perform Secure-mode initialization routines. */ - - /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled. - * Nordic SPU should handle Secure Attribution tasks */ + /* Perform Secure-mode initialization routines. */ + + /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled. + * Nordic SPU should handle Secure Attribution tasks */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); + SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); #endif - - /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_6()){ - NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); - NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); - } - - /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_14()){ - *((volatile uint32_t *)0x50004A38) = 0x01ul; - NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; - } - - /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_15()){ - NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; - } - - /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_20()){ - *((volatile uint32_t *)0x5003AEE4) = 0xE; - } - - /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf91_errata_31()){ - *((volatile uint32_t *)0x5000470Cul) = 0x0; - *((volatile uint32_t *)0x50004710ul) = 0x1; - } - - /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim - until one ADDR is not initialized. */ - uint32_t index = 0; - for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++){ - #if defined ( __ICCARM__ ) + + /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_6()) { + NRF_POWER_S->EVENTS_SLEEPENTER = + (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); + NRF_POWER_S->EVENTS_SLEEPEXIT = + (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); + } + + /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_14()) { + *((volatile uint32_t *)0x50004A38) = 0x01ul; + NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; + } + + /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_15()) { + NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; + } + + /* Workaround for Errata 20 "RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_20()) { + *((volatile uint32_t *)0x5003AEE4) = 0xE; + } + + /* Workaround for Errata 31 "XOSC32k Startup Failure" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/index.jsp */ + if (nrf91_errata_31()) { + *((volatile uint32_t *)0x5000470Cul) = 0x0; + *((volatile uint32_t *)0x50004710ul) = 0x1; + } + + /* Trimming of the device. Copy all the trimming values from FICR into the target addresses. Trim + until one ADDR is not initialized. */ + uint32_t index = 0; + for (index = 0; index < 256ul && NRF_FICR_S->TRIMCNF[index].ADDR != 0xFFFFFFFFul; index++) { + #if defined (__ICCARM__) #pragma diag_suppress=Pa082 #endif - *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA; - #if defined ( __ICCARM__ ) + *(volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA; + #if defined (__ICCARM__) #pragma diag_default=Pa082 #endif - } - - /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ - if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { - /* Wait for pending NVMC operations to finish */ - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Enable write mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - if (uicr_HFXOSRC_erased()){ + } + + /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ + if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { + /* Wait for pending NVMC operations to finish */ + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Enable write mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + if (uicr_HFXOSRC_erased()) { /* Write default value to UICR->HFXOSRC */ uicr_erased_value = NRF_UICR_S->HFXOSRC; uicr_new_value = (uicr_erased_value & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; NRF_UICR_S->HFXOSRC = uicr_new_value; while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - if (uicr_HFXOCNT_erased()){ + } + + if (uicr_HFXOCNT_erased()) { /* Write default value to UICR->HFXOCNT */ uicr_erased_value = NRF_UICR_S->HFXOCNT; uicr_new_value = (uicr_erased_value & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; NRF_UICR_S->HFXOCNT = uicr_new_value; while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - } - - /* Enable read mode in NVMC */ - NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - - /* Reset to apply clock select update */ - NVIC_SystemReset(); } - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product - Specification to see which ones). */ + /* Enable read mode in NVMC */ + NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + + /* Reset to apply clock select update */ + NVIC_SystemReset(); + } + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ #if defined (ENABLE_TRACE) - // Enable Trace And Debug peripheral - NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; - NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; - - // Set up Trace pads SPU firewall - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN); - NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN); - - // Configure trace port pads - NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; - NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; - - // Select trace pins - NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; - NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; - NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; - NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; - NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; - - // Set trace port speed to 32 MHz - NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; - - *((uint32_t *)(0xE0053000ul)) = 0x00000001ul; - - *((uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; - *((uint32_t *)(0xE005A004ul)) = 0x00000009ul; - *((uint32_t *)(0xE005A000ul)) = 0x00000303ul; - *((uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; - - *((uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; - *((uint32_t *)(0xE005B004ul)) = 0x00003000ul; - *((uint32_t *)(0xE005B000ul)) = 0x00000308ul; - *((uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; - - *((uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; - *((uint32_t *)(0xE0058000ul)) = 0x00000000ul; - *((uint32_t *)(0xE0058004ul)) = 0x00000000ul; - *((uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; - - /* Rom table does not list ETB, or TPIU base addresses. - * Some debug probes may require manual configuration of these peripherals to enable tracing. - * ETB_BASE = 0xE0051000 - * TPIU_BASE = 0xE0054000 - */ + /* Enable Trace And Debug peripheral */ + NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk; + NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk; + + /* Set up Trace pads SPU firewall */ + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACECLK_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA0_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA1_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA2_PIN); + NRF_SPU_S->GPIOPORT[0].PERM &= ~(1 << TRACE_TRACEDATA3_PIN); + + /* Configure trace port pads */ + NRF_P0_S->PIN_CNF[TRACE_TRACECLK_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA0_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA1_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA2_PIN] = TRACE_PIN_CNF_VALUE; + NRF_P0_S->PIN_CNF[TRACE_TRACEDATA3_PIN] = TRACE_PIN_CNF_VALUE; + + /* Select trace pins */ + NRF_TAD_S->PSEL.TRACECLK = TRACE_TRACECLK_PIN; + NRF_TAD_S->PSEL.TRACEDATA0 = TRACE_TRACEDATA0_PIN; + NRF_TAD_S->PSEL.TRACEDATA1 = TRACE_TRACEDATA1_PIN; + NRF_TAD_S->PSEL.TRACEDATA2 = TRACE_TRACEDATA2_PIN; + NRF_TAD_S->PSEL.TRACEDATA3 = TRACE_TRACEDATA3_PIN; + + /* Set trace port speed to 32 MHz */ + NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz; + + *((uint32_t *)(0xE0053000ul)) = 0x00000001ul; + + *((uint32_t *)(0xE005AFB0ul)) = 0xC5ACCE55ul; + *((uint32_t *)(0xE005A000ul)) &= 0xFFFFFF00ul; + *((uint32_t *)(0xE005A004ul)) = 0x00000009ul; + *((uint32_t *)(0xE005A000ul)) = 0x00000303ul; + *((uint32_t *)(0xE005AFB0ul)) = 0x00000000ul; + + *((uint32_t *)(0xE005BFB0ul)) = 0xC5ACCE55ul; + *((uint32_t *)(0xE005B000ul)) &= 0xFFFFFF00ul; + *((uint32_t *)(0xE005B004ul)) = 0x00003000ul; + *((uint32_t *)(0xE005B000ul)) = 0x00000308ul; + *((uint32_t *)(0xE005BFB0ul)) = 0x00000000ul; + + *((uint32_t *)(0xE0058FB0ul)) = 0xC5ACCE55ul; + *((uint32_t *)(0xE0058000ul)) = 0x00000000ul; + *((uint32_t *)(0xE0058004ul)) = 0x00000000ul; + *((uint32_t *)(0xE0058FB0ul)) = 0x00000000ul; + + /* Rom table does not list ETB, or TPIU base addresses. + * Some debug probes may require manual configuration of these peripherals to enable tracing. + * ETB_BASE = 0xE0051000 + * TPIU_BASE = 0xE0054000 + */ #endif - /* Allow Non-Secure code to run FPU instructions. - * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ - SCB->NSACR |= (3UL << 10); + /* Allow Non-Secure code to run FPU instructions. + * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ + SCB->NSACR |= (3UL << 10); #endif - + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); #endif - + SystemCoreClockUpdate(); NVIC_Relocate(); @@ -244,22 +248,24 @@ #if !defined(NRF_TRUSTZONE_NONSECURE) - bool uicr_HFXOCNT_erased() - { - if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) { - return true; - } - return false; - } - - - bool uicr_HFXOSRC_erased() - { - if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { - return true; - } - return false; - } +bool +uicr_HFXOCNT_erased() +{ + if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) { + return true; + } + return false; +} + + +bool +uicr_HFXOSRC_erased() +{ + if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + return true; + } + return false; +} #endif /*lint --flb "Leave library region" */ ``` </details> ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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