apache-mynewt-bot removed a comment on pull request #2368: URL: https://github.com/apache/mynewt-core/pull/2368#issuecomment-695954842
<!-- style-bot --> ## Style check summary ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md) #### hw/mcu/dialog/cmac/include/mcu/mcu.h <details> ```diff @@ -35,11 +35,13 @@ #define MCU_DIAG_MAP(_port, _word, _evt) \ CMAC->CM_DIAG_PORT ## _port ## _REG = \ (_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \ - (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos) + (CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos << \ + CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos) #define MCU_DIAG_MAP_BIT(_port, _word, _evt, _bit) \ CMAC->CM_DIAG_PORT ## _port ## _REG = \ (_word << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_WORD_Pos) | \ - ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos) + ((CMAC_CM_DIAG_WORD ## _word ## _REG_DIAG ## _word ## _ ## _evt ## _Pos + (_bit)) << \ + CMAC_CM_DIAG_PORT ## _port ## _REG_DIAG_BIT_Pos) /* Output diagnostic setial message */ #ifndef MCU_DIAG_SER_DISABLE ``` </details> #### hw/mcu/dialog/cmac/src/cmac_sleep.c <details> ```diff @@ -119,8 +119,8 @@ " bne 1b \n" : : [reg] "l" (retained_regs), - [val] "l" (g_retained_regs_val), - [idx] "l" (sizeof(retained_regs)) + [val] "l" (g_retained_regs_val), + [idx] "l" (sizeof(retained_regs)) : "r3", "r4", "memory"); } @@ -135,8 +135,8 @@ " bne 1b \n" : : [reg] "l" (retained_regs), - [val] "l" (g_retained_regs_val), - [idx] "l" (sizeof(retained_regs)) + [val] "l" (g_retained_regs_val), + [idx] "l" (sizeof(retained_regs)) : "r3", "r4", "memory"); } ``` </details> #### hw/mcu/dialog/cmac/src/cmac_timer.c <details> ```diff @@ -224,10 +224,10 @@ * Compiler barrier to make sure calculations are already done prior to * this line since code below has strict time constraints. */ - asm volatile("" - : - :"r" (comp_ll_timer_36), "r" (comp_ll_timer_09) - : "memory"); + asm volatile ("" + : + : "r" (comp_ll_timer_36), "r" (comp_ll_timer_09) + : "memory"); /* * Normally we should only wait for next 1MHz tick but since prior to ``` </details> #### hw/mcu/dialog/cmac/src/hal_system.c <details> ```diff @@ -37,12 +37,14 @@ __disable_irq(); if (hal_debugger_connected()) { - asm("bkpt"); + asm ("bkpt"); } CMAC->CM_EXC_STAT_REG = CMAC_CM_EXC_STAT_REG_EXC_FW_ERROR_Msk; - for (;;); + for (;;) { + ; + } } int ``` </details> #### hw/mcu/dialog/cmac/src/system_cmac.c <details> ```diff @@ -37,7 +37,9 @@ #if MYNEWT_VAL(MCU_DEBUG_SWD_WAIT_FOR_ATTACH) while (!hal_debugger_connected()); - for (int i = 0; i < 1000000; i++); + for (int i = 0; i < 1000000; i++) { + ; + } #endif CMAC->CM_CTRL_REG &= ~CMAC_CM_CTRL_REG_CM_BS_RESET_N_Msk; ``` </details> #### hw/mcu/dialog/include/CMAC.h <details> ```diff @@ -35,13 +35,13 @@ /** @addtogroup Dialog - * @{ - */ + * @{ + */ /** @addtogroup D2763x - * @{ - */ + * @{ + */ #ifndef D2763X_H @@ -71,13 +71,13 @@ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" #pragma clang diagnostic ignored "-Wnested-anon-types" #elif defined (__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif @@ -91,8 +91,8 @@ #endif /*CMSIS_STRIP_HEADER*/ /** @addtogroup Device_Peripheral_peripherals - * @{ - */ + * @{ + */ @@ -102,162 +102,162 @@ /** - * @brief CMAC registers (CMAC) - */ + * @brief CMAC registers (CMAC) + */ typedef struct { /*!< (@ 0x40000000) CMAC Structure */ - __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */ - __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */ - __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */ - __I uint32_t RESERVED; - __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */ - __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */ - __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */ - __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */ - __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */ - __I uint32_t RESERVED1[23]; - __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */ - __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */ - __I uint32_t RESERVED2[30]; - __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */ - __I uint32_t RESERVED3[3]; - __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */ - __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */ - __I uint32_t RESERVED4[2]; - __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */ - __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */ - __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */ - __I uint32_t RESERVED5[53]; - __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */ - __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */ - __I uint32_t RESERVED6[2]; - __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */ - __I uint32_t RESERVED7[3]; - __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */ - __I uint32_t RESERVED8[3]; - __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */ - __I uint32_t RESERVED9[51]; - __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */ - __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */ - __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */ - __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */ - __I uint32_t RESERVED10[8]; - __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */ - __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */ - __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */ - __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */ - __I uint32_t RESERVED11[2]; - __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */ - __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */ - __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */ - __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */ - __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */ - __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */ - __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */ - __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */ - __I uint32_t RESERVED12[294]; - __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */ - __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */ - __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */ - __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */ - __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */ - __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */ - __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */ - __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */ - __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */ - __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */ - __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */ - __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */ - __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */ - __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */ - __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */ - __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */ - __I uint32_t RESERVED13[16]; - __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */ - __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */ - __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */ - __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */ - __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */ - __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */ - __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */ - __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */ - __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */ - __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */ - __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */ - __I uint32_t RESERVED14[17]; - __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */ - __I uint32_t RESERVED15[3]; - __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */ - __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */ - __I uint32_t RESERVED16[446]; - __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */ - __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */ - __I uint32_t RESERVED17[2]; - __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */ - __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */ - __I uint32_t RESERVED18[2]; - __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */ - __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */ - __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */ - __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */ - __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */ - __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */ - __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */ - __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */ - __I uint32_t RESERVED19[48]; - __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */ - __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */ - __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */ - __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */ - __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */ - __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */ - __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */ - __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */ - __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */ - __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */ - __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */ - __I uint32_t RESERVED20[949]; - __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */ - __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */ - __I uint32_t RESERVED21[62]; - __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */ - __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */ - __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */ - __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */ + __IO uint32_t CM_CTRL_REG; /*!< (@ 0x00000000) CM_CTRL_REG */ + __IO uint32_t CM_STAT_REG; /*!< (@ 0x00000004) CM_STAT_REG */ + __IO uint32_t CM_CLK_COMP_REG; /*!< (@ 0x00000008) CM_CLK_COMP_REG */ + __I uint32_t RESERVED; + __IO uint32_t CM_EXC_STAT_REG; /*!< (@ 0x00000010) CM_EXC_STAT_REG */ + __IO uint32_t CM_EXC_DIS_REG; /*!< (@ 0x00000014) CM_EXC_DIS_REG */ + __IO uint32_t CM_EV_SET_REG; /*!< (@ 0x00000018) CM_EV_SET_REG */ + __IO uint32_t CM_EV_LATCHED_REG; /*!< (@ 0x0000001C) CM_EV_LATCHED_REG */ + __IO uint32_t CM_EV_LINKUP_REG; /*!< (@ 0x00000020) CM_EV_LINKUP_REG */ + __I uint32_t RESERVED1[23]; + __IO uint32_t CM_PHY_CTRL_REG; /*!< (@ 0x00000080) CM_PHY_CTRL_REG */ + __IO uint32_t CM_PHY_CTRL2_REG; /*!< (@ 0x00000084) CM_PHY_CTRL2_REG */ + __I uint32_t RESERVED2[30]; + __IO uint32_t CM_CTRL2_REG; /*!< (@ 0x00000100) CM_CTRL2_REG */ + __I uint32_t RESERVED3[3]; + __IO uint32_t CM_BS_WINDOW_REG; /*!< (@ 0x00000110) CM_BS_WINDOW_REG */ + __IO uint32_t CM_BS_WINDOW_CNT_REG; /*!< (@ 0x00000114) CM_BS_WINDOW_CNT_REG */ + __I uint32_t RESERVED4[2]; + __IO uint32_t CM_BS_SMPL_ST_REG; /*!< (@ 0x00000120) CM_BS_SMPL_ST_REG */ + __IO uint32_t CM_BS_SMPL_FST_REG; /*!< (@ 0x00000124) CM_BS_SMPL_FST_REG */ + __IO uint32_t CM_BS_SMPL_D_REG; /*!< (@ 0x00000128) CM_BS_SMPL_D_REG */ + __I uint32_t RESERVED5[53]; + __IO uint32_t CM_DMA_STAT_REG; /*!< (@ 0x00000200) CM_DMA_STAT_REG */ + __IO uint32_t CM_TS1_REG; /*!< (@ 0x00000204) CM_TS1_REG */ + __I uint32_t RESERVED6[2]; + __IO uint32_t CM_CRC_REG; /*!< (@ 0x00000210) CM_CRC_REG */ + __I uint32_t RESERVED7[3]; + __IO uint32_t CM_WHITENING_REG; /*!< (@ 0x00000220) CM_WHITENING_REG */ + __I uint32_t RESERVED8[3]; + __IO uint32_t CM_AOAD_REG; /*!< (@ 0x00000230) CM_AOAD_REG */ + __I uint32_t RESERVED9[51]; + __IO uint32_t CM_LL_INT_MSK_SET_REG; /*!< (@ 0x00000300) CM_LL_INT_MSK_SET_REG */ + __IO uint32_t CM_LL_INT_MSK_CLR_REG; /*!< (@ 0x00000304) CM_LL_INT_MSK_CLR_REG */ + __IO uint32_t CM_LL_INT_STAT_REG; /*!< (@ 0x00000308) CM_LL_INT_STAT_REG */ + __IO uint32_t CM_LL_INT_SEL_REG; /*!< (@ 0x0000030C) CM_LL_INT_SEL_REG */ + __I uint32_t RESERVED10[8]; + __IO uint32_t CM_LL_TIMER1_36_10_REG; /*!< (@ 0x00000330) CM_LL_TIMER1_36_10_REG */ + __IO uint32_t CM_LL_TIMER1_9_0_REG; /*!< (@ 0x00000334) CM_LL_TIMER1_9_0_REG */ + __IO uint32_t CM_LL_TIMER1_9_0_EQ_X_REG; /*!< (@ 0x00000338) CM_LL_TIMER1_9_0_EQ_X_REG */ + __IO uint32_t CM_LL_TIMER1_9_0_EQ_Y_REG; /*!< (@ 0x0000033C) CM_LL_TIMER1_9_0_EQ_Y_REG */ + __I uint32_t RESERVED11[2]; + __IO uint32_t CM_LL_TIMER1_36_10_EQ_X_REG; /*!< (@ 0x00000348) CM_LL_TIMER1_36_10_EQ_X_REG */ + __IO uint32_t CM_LL_TIMER1_36_10_EQ_Y_REG; /*!< (@ 0x0000034C) CM_LL_TIMER1_36_10_EQ_Y_REG */ + __IO uint32_t CM_LL_TIMER1_36_10_EQ_Z_REG; /*!< (@ 0x00000350) CM_LL_TIMER1_36_10_EQ_Z_REG */ + __IO uint32_t CM_LL_TIMER1_EQ_X_HI_REG; /*!< (@ 0x00000354) CM_LL_TIMER1_EQ_X_HI_REG */ + __IO uint32_t CM_LL_TIMER1_EQ_X_LO_REG; /*!< (@ 0x00000358) CM_LL_TIMER1_EQ_X_LO_REG */ + __IO uint32_t CM_LL_TIMER1_EQ_Y_HI_REG; /*!< (@ 0x0000035C) CM_LL_TIMER1_EQ_Y_HI_REG */ + __IO uint32_t CM_LL_TIMER1_EQ_Y_LO_REG; /*!< (@ 0x00000360) CM_LL_TIMER1_EQ_Y_LO_REG */ + __IO uint32_t CM_LL_TIMER1_EQ_Y_CTRL_REG; /*!< (@ 0x00000364) CM_LL_TIMER1_EQ_Y_CTRL_REG */ + __I uint32_t RESERVED12[294]; + __IO uint32_t CM_DIAG_PORT0_REG; /*!< (@ 0x00000800) CM_DIAG_PORT0_REG */ + __IO uint32_t CM_DIAG_PORT1_REG; /*!< (@ 0x00000804) CM_DIAG_PORT1_REG */ + __IO uint32_t CM_DIAG_PORT2_REG; /*!< (@ 0x00000808) CM_DIAG_PORT2_REG */ + __IO uint32_t CM_DIAG_PORT3_REG; /*!< (@ 0x0000080C) CM_DIAG_PORT3_REG */ + __IO uint32_t CM_DIAG_PORT4_REG; /*!< (@ 0x00000810) CM_DIAG_PORT4_REG */ + __IO uint32_t CM_DIAG_PORT5_REG; /*!< (@ 0x00000814) CM_DIAG_PORT5_REG */ + __IO uint32_t CM_DIAG_PORT6_REG; /*!< (@ 0x00000818) CM_DIAG_PORT6_REG */ + __IO uint32_t CM_DIAG_PORT7_REG; /*!< (@ 0x0000081C) CM_DIAG_PORT7_REG */ + __IO uint32_t CM_DIAG_PORT8_REG; /*!< (@ 0x00000820) CM_DIAG_PORT8_REG */ + __IO uint32_t CM_DIAG_PORT9_REG; /*!< (@ 0x00000824) CM_DIAG_PORT9_REG */ + __IO uint32_t CM_DIAG_PORT10_REG; /*!< (@ 0x00000828) CM_DIAG_PORT10_REG */ + __IO uint32_t CM_DIAG_PORT11_REG; /*!< (@ 0x0000082C) CM_DIAG_PORT11_REG */ + __IO uint32_t CM_DIAG_PORT12_REG; /*!< (@ 0x00000830) CM_DIAG_PORT12_REG */ + __IO uint32_t CM_DIAG_PORT13_REG; /*!< (@ 0x00000834) CM_DIAG_PORT13_REG */ + __IO uint32_t CM_DIAG_PORT14_REG; /*!< (@ 0x00000838) CM_DIAG_PORT14_REG */ + __IO uint32_t CM_DIAG_PORT15_REG; /*!< (@ 0x0000083C) CM_DIAG_PORT15_REG */ + __I uint32_t RESERVED13[16]; + __IO uint32_t CM_DIAG_WORD0_REG; /*!< (@ 0x00000880) CM_DIAG_WORD0_REG */ + __IO uint32_t CM_DIAG_WORD1_REG; /*!< (@ 0x00000884) CM_DIAG_WORD1_REG */ + __IO uint32_t CM_DIAG_WORD2_REG; /*!< (@ 0x00000888) CM_DIAG_WORD2_REG */ + __IO uint32_t CM_DIAG_WORD3_REG; /*!< (@ 0x0000088C) CM_DIAG_WORD3_REG */ + __IO uint32_t CM_DIAG_WORD4_REG; /*!< (@ 0x00000890) CM_DIAG_WORD4_REG */ + __IO uint32_t CM_DIAG_WORD5_REG; /*!< (@ 0x00000894) CM_DIAG_WORD5_REG */ + __IO uint32_t CM_DIAG_WORD6_REG; /*!< (@ 0x00000898) CM_DIAG_WORD6_REG */ + __IO uint32_t CM_DIAG_WORD7_REG; /*!< (@ 0x0000089C) CM_DIAG_WORD7_REG */ + __IO uint32_t CM_DIAG_WORD8_REG; /*!< (@ 0x000008A0) CM_DIAG_WORD8_REG */ + __IO uint32_t CM_DIAG_WORD9_REG; /*!< (@ 0x000008A4) CM_DIAG_WORD9_REG */ + __IO uint32_t CM_DIAG_WORD10_REG; /*!< (@ 0x000008A8) CM_DIAG_WORD10_REG */ + __I uint32_t RESERVED14[17]; + __IO uint32_t CM_DIAG_DSER_REG; /*!< (@ 0x000008F0) CM_DIAG_DSER_REG */ + __I uint32_t RESERVED15[3]; + __IO uint32_t CM_ERROR_REG; /*!< (@ 0x00000900) CM_ERROR_REG */ + __IO uint32_t CM_ERROR_DIS_REG; /*!< (@ 0x00000904) CM_ERROR_DIS_REG */ + __I uint32_t RESERVED16[446]; + __IO uint32_t CM_FRAME_1_REG; /*!< (@ 0x00001000) CM_FRAME_1_REG */ + __IO uint32_t CM_FRAME_2_REG; /*!< (@ 0x00001004) CM_FRAME_2_REG */ + __I uint32_t RESERVED17[2]; + __IO uint32_t CM_FIELD_PUSH_DATA_REG; /*!< (@ 0x00001010) CM_FIELD_PUSH_DATA_REG */ + __IO uint32_t CM_FIELD_PUSH_CTRL_REG; /*!< (@ 0x00001014) CM_FIELD_PUSH_CTRL_REG */ + __I uint32_t RESERVED18[2]; + __IO uint32_t CM_FIELD_1_DATA_REG; /*!< (@ 0x00001020) CM_FIELD_1_DATA_REG */ + __IO uint32_t CM_FIELD_1_CTRL_REG; /*!< (@ 0x00001024) CM_FIELD_1_CTRL_REG */ + __IO uint32_t CM_FIELD_2_DATA_REG; /*!< (@ 0x00001028) CM_FIELD_2_DATA_REG */ + __IO uint32_t CM_FIELD_2_CTRL_REG; /*!< (@ 0x0000102C) CM_FIELD_2_CTRL_REG */ + __IO uint32_t CM_FIELD_3_DATA_REG; /*!< (@ 0x00001030) CM_FIELD_3_DATA_REG */ + __IO uint32_t CM_FIELD_3_CTRL_REG; /*!< (@ 0x00001034) CM_FIELD_3_CTRL_REG */ + __IO uint32_t CM_FIELD_4_DATA_REG; /*!< (@ 0x00001038) CM_FIELD_4_DATA_REG */ + __IO uint32_t CM_FIELD_4_CTRL_REG; /*!< (@ 0x0000103C) CM_FIELD_4_CTRL_REG */ + __I uint32_t RESERVED19[48]; + __IO uint32_t CM_CRYPTO_CTRL_REG; /*!< (@ 0x00001100) CM_CRYPTO_CTRL_REG */ + __IO uint32_t CM_CRYPTO_STAT_REG; /*!< (@ 0x00001104) CM_CRYPTO_STAT_REG */ + __IO uint32_t CM_CRYPTO_KEY_31_0_REG; /*!< (@ 0x00001108) CM_CRYPTO_KEY_31_0_REG */ + __IO uint32_t CM_CRYPTO_KEY_63_32_REG; /*!< (@ 0x0000110C) CM_CRYPTO_KEY_63_32_REG */ + __IO uint32_t CM_CRYPTO_KEY_95_64_REG; /*!< (@ 0x00001110) CM_CRYPTO_KEY_95_64_REG */ + __IO uint32_t CM_CRYPTO_KEY_127_96_REG; /*!< (@ 0x00001114) CM_CRYPTO_KEY_127_96_REG */ + __IO uint32_t CM_CRYPTO_IN_ADR0_REG; /*!< (@ 0x00001118) CM_CRYPTO_IN_ADR0_REG */ + __IO uint32_t CM_CRYPTO_IN_ADR1_REG; /*!< (@ 0x0000111C) CM_CRYPTO_IN_ADR1_REG */ + __IO uint32_t CM_CRYPTO_IN_ADR2_REG; /*!< (@ 0x00001120) CM_CRYPTO_IN_ADR2_REG */ + __IO uint32_t CM_CRYPTO_IN_ADR3_REG; /*!< (@ 0x00001124) CM_CRYPTO_IN_ADR3_REG */ + __IO uint32_t CM_CRYPTO_OUT_ADR_REG; /*!< (@ 0x00001128) CM_CRYPTO_OUT_ADR_REG */ + __I uint32_t RESERVED20[949]; + __IO uint32_t CM_CTRL_SYS_REG; /*!< (@ 0x40002000) CMAC and System Control Register */ + __IO uint32_t CM_WDOG_REG; /*!< (@ 0x40002004) CMAC Watch Dog Control Register */ + __I uint32_t RESERVED21[62]; + __IO uint32_t CM_DIAG_IRQ1_WORD_REG; /*!< (@ 0x40002100) Diagnostic IRQ on Word1 - Word1 Register */ + __IO uint32_t CM_DIAG_IRQ1_EDGE_REG; /*!< (@ 0x40002104) Diagnostic IRQ on Word1 - Edge Register */ + __IO uint32_t CM_DIAG_IRQ1_STAT_REG; /*!< (@ 0x40002108) Diagnostic IRQ on Word1 - Status Register */ + __IO uint32_t CM_DIAG_IRQ1_MASK_REG; /*!< (@ 0x4000210C) Diagnostic IRQ on Word1 - Mask Register */ } CMAC_Type; /*!< Size = 4396 (0x112c) */ typedef struct { /*!< (@ 0x50010400) CMAC_TIMER_SLP Structure */ - __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */ - __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */ - __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */ + __IO uint32_t CM_SLP_CTRL_REG; /*!< (@ 0x50010400) CMAC Sleep Control 1 (allowed to RMW) */ + __IO uint32_t CM_SLP_CTRL2_REG; /*!< (@ 0x50010404) CMAC Sleep Control 2 (no RMW) */ + __IO uint32_t CM_SLP_TIMER_REG; /*!< (@ 0x50010408) CMAC Sleep Timer */ } CMAC_TIMER_SLP_Type; typedef struct { /*!< (@ 0x50000200) PDC Structure */ - __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */ - __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */ - __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */ - __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */ - __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */ - __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */ - __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */ - __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */ - __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */ - __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */ - __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */ - __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */ - __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */ - __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */ - __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */ - __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */ - __IM uint32_t RESERVED[16]; - __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */ - __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */ - __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */ - __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */ - __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */ - __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */ + __IOM uint32_t PDC_CTRL0_REG; /*!< (@ 0x00000000) PDC control register */ + __IOM uint32_t PDC_CTRL1_REG; /*!< (@ 0x00000004) PDC control register */ + __IOM uint32_t PDC_CTRL2_REG; /*!< (@ 0x00000008) PDC control register */ + __IOM uint32_t PDC_CTRL3_REG; /*!< (@ 0x0000000C) PDC control register */ + __IOM uint32_t PDC_CTRL4_REG; /*!< (@ 0x00000010) PDC control register */ + __IOM uint32_t PDC_CTRL5_REG; /*!< (@ 0x00000014) PDC control register */ + __IOM uint32_t PDC_CTRL6_REG; /*!< (@ 0x00000018) PDC control register */ + __IOM uint32_t PDC_CTRL7_REG; /*!< (@ 0x0000001C) PDC control register */ + __IOM uint32_t PDC_CTRL8_REG; /*!< (@ 0x00000020) PDC control register */ + __IOM uint32_t PDC_CTRL9_REG; /*!< (@ 0x00000024) PDC control register */ + __IOM uint32_t PDC_CTRL10_REG; /*!< (@ 0x00000028) PDC control register */ + __IOM uint32_t PDC_CTRL11_REG; /*!< (@ 0x0000002C) PDC control register */ + __IOM uint32_t PDC_CTRL12_REG; /*!< (@ 0x00000030) PDC control register */ + __IOM uint32_t PDC_CTRL13_REG; /*!< (@ 0x00000034) PDC control register */ + __IOM uint32_t PDC_CTRL14_REG; /*!< (@ 0x00000038) PDC control register */ + __IOM uint32_t PDC_CTRL15_REG; /*!< (@ 0x0000003C) PDC control register */ + __IM uint32_t RESERVED[16]; + __IOM uint32_t PDC_ACKNOWLEDGE_REG; /*!< (@ 0x00000080) Clear a pending PDC bit */ + __IOM uint32_t PDC_PENDING_REG; /*!< (@ 0x00000084) Shows any pending wakup event */ + __IOM uint32_t PDC_PENDING_SNC_REG; /*!< (@ 0x00000088) Shows any pending IRQ to SNC */ + __IOM uint32_t PDC_PENDING_CM33_REG; /*!< (@ 0x0000008C) Shows any pending IRQ to CM33 */ + __IOM uint32_t PDC_PENDING_CMAC_REG; /*!< (@ 0x00000090) Shows any pending IRQ to CM33 */ + __IOM uint32_t PDC_SET_PENDING_REG; /*!< (@ 0x00000094) Set a pending PDC bit */ } PDC_Type; /*!< Size = 152 (0x98) */ @@ -270,8 +270,8 @@ /** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ + * @{ + */ #define CMAC_BASE 0x40000000UL #define CMAC_TIMER_SLP_BASE 0x50010400UL @@ -286,12 +286,12 @@ /** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define CMAC ((CMAC_Type*) CMAC_BASE) + * @{ + */ + +#define CMAC ((CMAC_Type *) CMAC_BASE) #define CMAC_TIMER_SLP ((CMAC_TIMER_SLP_Type *) CMAC_TIMER_SLP_BASE) -#define PDC ((PDC_Type*) PDC_BASE) +#define PDC ((PDC_Type *) PDC_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -300,17 +300,17 @@ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) - /* leave anonymous unions enabled */ +/* leave anonymous unions enabled */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #endif @@ -320,8 +320,8 @@ /** @addtogroup PosMask_peripherals - * @{ - */ + * @{ + */ ``` </details> #### hw/mcu/dialog/include/system_CMAC.h <details> ```diff @@ -28,7 +28,7 @@ #ifndef _SYSTEM_D2763_INCLUDED #define _SYSTEM_D2763_INCLUDED -// From datasheet.h: +/* From datasheet.h: */ /*--GPIO PID functions-------------------------------------------------------------------------*/ #define FUNC_GPIO (0) @@ -98,73 +98,73 @@ #define DIR_PULLDOWN 0x200 #define DIR_OUTPUT 0x300 -// code copied from global_functions.h +/* code copied from global_functions.h */ #if defined(CORTEX_M33) typedef enum { /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* ========================================== DA1469x Specific Interrupt Numbers =========================================== */ - SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */ - DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */ - CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */ - CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */ - CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */ - UART_IRQn = 5, /*!< 5 UART interrupt request. */ - UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */ - UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */ - I2C_IRQn = 8, /*!< 8 I2C interrupt request. */ - I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */ - SPI_IRQn = 10, /*!< 10 SPI interrupt request. */ - SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */ - RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */ - RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */ - RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */ - USB_IRQn = 15, /*!< 15 USB interrupt request. */ - TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */ - TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */ - RTC_IRQn = 18, /*!< 18 RTC interrupt request. */ - KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */ - PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */ - VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */ - MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */ - DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */ - TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */ - DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */ - XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */ - GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */ - SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */ - CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */ - CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */ - RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */ - RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */ - PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */ - TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */ - TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */ - LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */ - RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */ - GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */ - GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */ - SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */ - RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */ - RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */ - RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */ - RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */ - RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */ - RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */ - RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */ + SNC_IRQn = 0, /*!< 0 Sensor Node Controller interrupt request. */ + DMA_IRQn = 1, /*!< 1 General Purpose DMA interrupt request. */ + CHARGER_STATE_IRQn = 2, /*!< 2 Charger State interrupt request. */ + CHARGER_ERROR_IRQn = 3, /*!< 3 Charger Error interrupt request. */ + CMAC2SYS_IRQn = 4, /*!< 4 CMAC and mailbox interrupt request. */ + UART_IRQn = 5, /*!< 5 UART interrupt request. */ + UART2_IRQn = 6, /*!< 6 UART2 interrupt request. */ + UART3_IRQn = 7, /*!< 7 UART3 interrupt request. */ + I2C_IRQn = 8, /*!< 8 I2C interrupt request. */ + I2C2_IRQn = 9, /*!< 9 I2C2 interrupt request. */ + SPI_IRQn = 10, /*!< 10 SPI interrupt request. */ + SPI2_IRQn = 11, /*!< 11 SPI2 interrupt request. */ + RESERVED12_IRQn = 12, /*!< 12 SoftWare interrupt request. */ + RESERVED13_IRQn = 13, /*!< 13 SoftWare interrupt request. */ + RESERVED14_IRQn = 14, /*!< 14 SoftWare interrupt request. */ + USB_IRQn = 15, /*!< 15 USB interrupt request. */ + TIMER_IRQn = 16, /*!< 16 TIMER interrupt request. */ + TIMER2_IRQn = 17, /*!< 17 TIMER2 interrupt request. */ + RTC_IRQn = 18, /*!< 18 RTC interrupt request. */ + KEY_WKUP_GPIO_IRQn = 19, /*!< 19 Debounced button press interrupt request. */ + PDC_IRQn = 20, /*!< 20 Wakeup IRQ from PDC to CM33 */ + VBUS_IRQn = 21, /*!< 21 VBUS presence interrupt request. */ + MRM_IRQn = 22, /*!< 22 Cache Miss Rate Monitor interrupt request. */ + DCDC_BOOST_IRQn = 23, /*!< 23 DCDC Boost interrupt request. */ + TRNG_IRQn = 24, /*!< 24 True Random Number Generation interrupt request. */ + DCDC_IRQn = 25, /*!< 25 DCDC interrupt request. */ + XTAL32M_RDY_IRQn = 26, /*!< 26 XTAL32M trimmed and ready interrupt request. */ + GPADC_IRQn = 27, /*!< 27 General Purpose Analog-Digital Converter interrupt request. */ + SDADC_IRQn = 28, /*!< 28 Sigma Delta Analog-Digital Converter interrupt request. */ + CRYPTO_IRQn = 29, /*!< 29 Crypto interrupt request. */ + CAPTIMER_IRQn = 30, /*!< 30 GPIO triggered Timer Capture interrupt request. */ + RFDIAG_IRQn = 31, /*!< 31 Baseband or Radio Diagnostics interrupt request. */ + RESERVED32_IRQn = 32, /*!< 32 SoftWare interrupt request. */ + PLL_LOCK_IRQn = 33, /*!< 33 Pll lock interrupt request. */ + TIMER3_IRQn = 34, /*!< 34 TIMER3 interrupt request. */ + TIMER4_IRQn = 35, /*!< 35 TIMER4 interrupt request. */ + LRA_IRQn = 36, /*!< 36 LRA/ERM interrupt request. */ + RTC_EVENT_IRQn = 37, /*!< 37 RTC event interrupt request. */ + GPIO_P0_IRQn = 38, /*!< 38 GPIO port 0 toggle interrupt request. */ + GPIO_P1_IRQn = 39, /*!< 39 GPIO port 1 toggle interrupt request. */ + SWIC_IRQn = 40, /*!< 40 Single Wire Interface Controller interrupt request. */ + RESERVED41_IRQn = 41, /*!< 41 SoftWare interrupt request. */ + RESERVED42_IRQn = 42, /*!< 42 SoftWare interrupt request. */ + RESERVED43_IRQn = 43, /*!< 43 SoftWare interrupt request. */ + RESERVED44_IRQn = 44, /*!< 44 SoftWare interrupt request. */ + RESERVED45_IRQn = 45, /*!< 45 SoftWare interrupt request. */ + RESERVED46_IRQn = 46, /*!< 46 SoftWare interrupt request. */ + RESERVED47_IRQn = 47 /*!< 47 SoftWare interrupt request. */ } IRQn_Type; @@ -184,45 +184,47 @@ #include "cmsis_mtb.h" #endif -#else // if defined(CORTEX_M0PLUS) +#else /* if defined(CORTEX_M0PLUS) */ typedef enum IRQn { /****** Cortex-M0 Processor Exceptions Numbers *****************************************/ -NMI_IRQn = -14, /* 2 Non Maskable Interrupt. */ -HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt. */ -SVCall_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt. */ -PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt. */ -SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt. */ + NMI_IRQn = -14,/* 2 Non Maskable Interrupt. */ + HardFault_IRQn = -13,/* 3 Cortex-M0 Hard Fault Interrupt. */ + SVCall_IRQn = -5,/* 11 Cortex-M0 SV Call Interrupt. */ + PendSV_IRQn = -2,/* 14 Cortex-M0 Pend SV Interrupt. */ + SysTick_IRQn = -1,/* 15 Cortex-M0 System Tick Interrupt. */ /****** CMAC CM0P Specific Interrupt Numbers *******************************************/ -FIELD_IRQn = 0, -CALLBACK_IRQn = 1, -FRAME_IRQn = 2, -DIAG_IRQn = 3, -HW_GEN_IRQn = 4, -SW_MAC_IRQn = 5, -LL_TIMER2PRMTV_IRQn = 6, -LL_TIMER2LLC_IRQn = 7, -CRYPTO_IRQn = 8, -SW_LLC_1_IRQn = 9, -SW_LLC_2_IRQn = 10, -SW_LLC_3_IRQn = 11, -SYS2CMAC_IRQn = 12 + FIELD_IRQn = 0, + CALLBACK_IRQn = 1, + FRAME_IRQn = 2, + DIAG_IRQn = 3, + HW_GEN_IRQn = 4, + SW_MAC_IRQn = 5, + LL_TIMER2PRMTV_IRQn = 6, + LL_TIMER2LLC_IRQn = 7, + CRYPTO_IRQn = 8, + SW_LLC_1_IRQn = 9, + SW_LLC_2_IRQn = 10, + SW_LLC_3_IRQn = 11, + SYS2CMAC_IRQn = 12 } IRQn_Type; /* Configuration of the Cortex-M0+ Processor and Core Peripherals */ #define __CM0_REV 0x0000 /*!< Core Revision r2p1 */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -//#define __MPU_PRESENT 1 /*!< MPU present or not */ -//#define __VTOR_PRESENT 1 /*!< Cortex-M0+ can support the VTOR */ +/* + #define __MPU_PRESENT 1 / *!< MPU present or not * / + #define __VTOR_PRESENT 1 / *!< Cortex-M0+ can support the VTOR * / + */ #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -//#include "system_CMSDK_CM0plus.h" /* CMSDK_CM0plus System include file */ - - -#endif // if defined(CORTEX_M0PLUS) - -// non-core specific code: +/*#include "system_CMSDK_CM0plus.h" / * CMSDK_CM0plus System include file * / */ + + +#endif /* if defined(CORTEX_M0PLUS) */ + +/* non-core specific code: */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I @@ -248,13 +250,13 @@ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" #pragma clang diagnostic ignored "-Wnested-anon-types" #elif defined (__GNUC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TMS470__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +/* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif @@ -264,4 +266,4 @@ -#endif //_SYSTEM_D2763_INCLUDED +#endif /*_SYSTEM_D2763_INCLUDED */ ``` </details> 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