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jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 8e2c5aeb5aac0a3c7886bc7af4b5b1643c2f494d
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Thu Oct 6 19:13:43 2022 +0200
mcu/stm32f7: Add way to enable DCache
STM32F7 do have Arm data cache.
This change add syscfg value that allows to enable this cache
and code that will enable it during startup.
DCache is not enabled by default for AXI bus to avoid crashes
till relocated vector table stays in SRAM1.
---
hw/mcu/stm/stm32f7xx/src/clock_stm32f7xx.c | 3 +++
hw/mcu/stm/stm32f7xx/syscfg.yml | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/hw/mcu/stm/stm32f7xx/src/clock_stm32f7xx.c
b/hw/mcu/stm/stm32f7xx/src/clock_stm32f7xx.c
index 8ff91bd45..0a6ce4f30 100644
--- a/hw/mcu/stm/stm32f7xx/src/clock_stm32f7xx.c
+++ b/hw/mcu/stm/stm32f7xx/src/clock_stm32f7xx.c
@@ -54,6 +54,9 @@ SystemClock_Config(void)
SCB_EnableICache();
#endif
+#if MYNEWT_VAL(STM32_ENABLE_DCACHE)
+ SCB_EnableDCache();
+#endif
/*
* Enable Power Control clock
*/
diff --git a/hw/mcu/stm/stm32f7xx/syscfg.yml b/hw/mcu/stm/stm32f7xx/syscfg.yml
index 9e42fb5ae..9ba4dd0ab 100644
--- a/hw/mcu/stm/stm32f7xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f7xx/syscfg.yml
@@ -31,6 +31,10 @@ syscfg.defs:
description: Enable instruction caching
value: 1
+ STM32_ENABLE_DCACHE:
+ description: Enable instruction caching
+ value: 0
+
STM32_CLOCK_VOLTAGESCALING_CONFIG:
description: Voltage scale
value: 0
