This is an automated email from the ASF dual-hosted git repository. andk pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/mynewt-nimble.git
The following commit(s) were added to refs/heads/master by this push: new c514f5b5 nimble/phy/cmac: Apply preferred RF setting per silicon variant (TSMC and GF). c514f5b5 is described below commit c514f5b574e425e34448f7843f7cd81dce49343a Author: ikaracha <ioannis.karachalios...@renesas.com> AuthorDate: Thu May 4 13:10:51 2023 +0300 nimble/phy/cmac: Apply preferred RF setting per silicon variant (TSMC and GF). --- nimble/drivers/dialog_cmac/src/ble_rf.c | 35 ++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/nimble/drivers/dialog_cmac/src/ble_rf.c b/nimble/drivers/dialog_cmac/src/ble_rf.c index 61f3663e..32ae0634 100644 --- a/nimble/drivers/dialog_cmac/src/ble_rf.c +++ b/nimble/drivers/dialog_cmac/src/ble_rf.c @@ -30,6 +30,14 @@ #define RF_CALIBRATION_1 (0x02) #define RF_CALIBRATION_2 (0x04) +enum chip_variant { + CHIP_VARIANT_TSMC, + CHIP_VARIANT_GF, + CHIP_VARIANT_UNKNOWN +}; + +static int g_chip_variant; + static const int8_t g_ble_rf_power_lvls[] = { -18, -12, -8, -6, -3, -2, -1, 0, 1, 2, 3, 4, 4, 5, 6 }; @@ -114,6 +122,21 @@ set_reg16_mask(uint32_t addr, uint16_t mask, uint16_t val) *reg = (*reg & (~mask)) | (val & mask); } +static inline int +read_chip_variant(void) +{ + uint32_t chip_id1 = get_reg32_bits(0x50040200, 0xFF); + + switch (chip_id1) { + case '2': + return CHIP_VARIANT_TSMC; + case '3': + return CHIP_VARIANT_GF; + default: + return CHIP_VARIANT_UNKNOWN; + } +} + static void delay_us(uint32_t delay_us) { @@ -233,6 +256,9 @@ ble_rf_synth_is_enabled(void) static void ble_rf_synth_apply_recommended_settings(void) { + if (g_chip_variant == CHIP_VARIANT_GF) { + set_reg32_mask(0x40022034, 0x00000018, 0x0215807B); + } set_reg32_mask(0x40022048, 0x0000000c, 0x000000d5); set_reg32_mask(0x40022050, 0x00000300, 0x00000300); set_reg16_mask(0x40022024, 0x0001, 0x0001); @@ -335,7 +361,11 @@ ble_rf_calibration_1(void) set_reg32(0x40020000, 0x0f168820); set_reg32_bits(0x40022000, 0x00000001, 0); set_reg32_bits(0x4002101c, 0x00001e00, 0); - set_reg32_bits(0x4002001c, 0x0000003f, 47); + if (g_chip_variant == CHIP_VARIANT_TSMC) { + set_reg32_bits(0x4002001c, 0x0000003f, 47); + } else { + set_reg32_bits(0x4002001c, 0x0000003f, 44); + } set_reg8(0x40020006, 1); set_reg32(0x40020020, 16); set_reg32_bits(0x4002003c, 0x00000800, 1); @@ -537,6 +567,9 @@ ble_rf_init(void) static bool done = false; uint32_t val; + g_chip_variant = read_chip_variant(); + assert(g_chip_variant != CHIP_VARIANT_UNKNOWN); + ble_rf_disable(); if (done) {