This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit cc41f5ec6f9306131bcc1dd6579c2d38443945a9
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Thu Feb 1 08:52:32 2024 +0100
hw/mcu: Add support for STM32G0
This add code for STM32G0 family.
Existing HAL was modified to accommodate to G0
hardware specifics.
MCU uses autogenerated linker script
Signed-off-by: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
---
hw/mcu/stm/stm32_common/src/hal_gpio.c | 14 +-
hw/mcu/stm/stm32_common/src/hal_os_tick.c | 11 +-
hw/mcu/stm/stm32_common/src/hal_spi.c | 13 +-
hw/mcu/stm/stm32_common/src/hal_uart.c | 12 +-
hw/mcu/stm/stm32_common/src/hal_watchdog.c | 4 +
hw/mcu/stm/stm32g0xx/include/mcu/cmsis_nvic.h | 34 +++
hw/mcu/stm/stm32g0xx/include/mcu/cortex_m0.h | 39 +++
hw/mcu/stm/stm32g0xx/include/mcu/mcu.h | 38 +++
hw/mcu/stm/stm32g0xx/include/mcu/mcu_vectors.h | 46 ++++
hw/mcu/stm/stm32g0xx/include/mcu/stm32_hal.h | 96 +++++++
hw/mcu/stm/stm32g0xx/include/mcu/stm32g0_bsp.h | 57 ++++
.../stm32g0xx/include/mcu/stm32g0xx_mynewt_hal.h | 67 +++++
.../include/mcu/vectors/stm32g030xx_vectors.h | 65 +++++
.../include/mcu/vectors/stm32g031xx_vectors.h | 66 +++++
.../include/mcu/vectors/stm32g041xx_vectors.h | 67 +++++
.../include/mcu/vectors/stm32g050xx_vectors.h | 64 +++++
.../include/mcu/vectors/stm32g051xx_vectors.h | 65 +++++
.../include/mcu/vectors/stm32g061xx_vectors.h | 67 +++++
.../include/mcu/vectors/stm32g070xx_vectors.h | 65 +++++
.../include/mcu/vectors/stm32g071xx_vectors.h | 66 +++++
.../include/mcu/vectors/stm32g081xx_vectors.h | 67 +++++
.../include/mcu/vectors/stm32g0b0xx_vectors.h | 65 +++++
.../include/mcu/vectors/stm32g0b1xx_vectors.h | 66 +++++
.../include/mcu/vectors/stm32g0c1xx_vectors.h | 67 +++++
hw/mcu/stm/stm32g0xx/pkg.yml | 65 +++++
hw/mcu/stm/stm32g0xx/src/clock_stm32g0xx.c | 251 +++++++++++++++++
hw/mcu/stm/stm32g0xx/src/hal_flash.c | 56 ++++
hw/mcu/stm/stm32g0xx/src/hal_reset_cause.c | 46 ++++
hw/mcu/stm/stm32g0xx/src/hal_system_init.c | 53 ++++
hw/mcu/stm/stm32g0xx/src/hal_timer_freq.c | 84 ++++++
hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c | 306 +++++++++++++++++++++
hw/mcu/stm/stm32g0xx/syscfg.yml | 149 ++++++++++
32 files changed, 2217 insertions(+), 14 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c
b/hw/mcu/stm/stm32_common/src/hal_gpio.c
index 002a6be05..93378ccd3 100644
--- a/hw/mcu/stm/stm32_common/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c
@@ -136,7 +136,7 @@ static struct gpio_irq_obj gpio_irq_handlers[16];
struct ext_irqs
{
-#if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0)
+#if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0) &&
!MYNEWT_VAL(MCU_STM32G0)
volatile uint32_t irq0;
volatile uint32_t irq1;
volatile uint32_t irq2;
@@ -185,7 +185,7 @@ ext_irq_handler(int index)
}
}
-#if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0)
+#if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0) &&
!MYNEWT_VAL(MCU_STM32G0)
/* External interrupt 0 */
static void
ext_irq0(void)
@@ -492,7 +492,7 @@ hal_gpio_pin_to_irq(int pin)
index = MCU_GPIO_PIN_NUM(pin);
-#if defined(STM32L0) || defined(STM32F0)
+#if defined(STM32L0) || defined(STM32F0) || defined(STM32G0)
if (index <= 1) {
irqn = EXTI0_1_IRQn;
} else if (index <= 3) {
@@ -525,7 +525,7 @@ hal_gpio_set_nvic(IRQn_Type irqn)
uint32_t isr;
switch (irqn) {
-#if MYNEWT_VAL(MCU_STM32L0) || MYNEWT_VAL(MCU_STM32F0)
+#if MYNEWT_VAL(MCU_STM32L0) || MYNEWT_VAL(MCU_STM32F0) || defined(STM32G0)
case EXTI0_1_IRQn:
isr = (uint32_t)&ext_irq0_1;
break;
@@ -971,7 +971,8 @@ hal_gpio_irq_enable(int pin)
mask = GPIO_MASK(pin);
__HAL_DISABLE_INTERRUPTS(ctx);
-#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) ||
MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5)
+#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) ||
MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \
+ MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0)
EXTI->IMR1 |= mask;
#else
EXTI->IMR |= mask;
@@ -993,7 +994,8 @@ hal_gpio_irq_disable(int pin)
mask = GPIO_MASK(pin);
__HAL_DISABLE_INTERRUPTS(ctx);
-#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) ||
MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5)
+#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) ||
MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \
+ MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0)
EXTI->IMR1 |= mask;
#else
EXTI->IMR &= ~mask;
diff --git a/hw/mcu/stm/stm32_common/src/hal_os_tick.c
b/hw/mcu/stm/stm32_common/src/hal_os_tick.c
index 166709f8a..1b167092c 100644
--- a/hw/mcu/stm/stm32_common/src/hal_os_tick.c
+++ b/hw/mcu/stm/stm32_common/src/hal_os_tick.c
@@ -71,6 +71,8 @@ __WFI(void)
#if defined(STM32L0) || defined(STM32F0) || defined(STM32U5)
#define RTC_IRQ RTC_IRQn
+#elif defined(STM32G0)
+#define RTC_IRQ RTC_TAMP_IRQn
#else
#define RTC_IRQ RTC_Alarm_IRQn
#endif
@@ -337,7 +339,12 @@ os_tick_init(uint32_t os_ticks_per_sec, int prio)
__HAL_DBGMCU_FREEZE_RTC();
-#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5)
+#if MYNEWT_VAL(MCU_STM32H7)
+ DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEPD1 | DBGMCU_CR_DBG_STOPD1 |
DBGMCU_CR_DBG_STANDBYD1);
+#elif MYNEWT_VAL(MCU_STM32G0)
+ __DBGMCU_CLK_ENABLE();
+ DBG->CR |= (DBG_CR_DBG_STOP | DBG_CR_DBG_STANDBY);
+#elif MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5) ||
MYNEWT_VAL(MCU_STM32H5)
DBGMCU->CR |= (DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY);
#else
DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP |
DBGMCU_CR_DBG_STANDBY);
@@ -405,6 +412,8 @@ os_tick_init(uint32_t os_ticks_per_sec, int prio)
DBGMCU->CR |= (DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY);
#elif MYNEWT_VAL(MCU_STM32H7)
DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEPD1 | DBGMCU_CR_DBG_STOPD1 |
DBGMCU_CR_DBG_STANDBYD1);
+#elif MYNEWT_VAL(MCU_STM32G0)
+ DBG->CR |= (DBG_CR_DBG_STOP | DBG_CR_DBG_STANDBY);
#else
DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP |
DBGMCU_CR_DBG_STANDBY);
#endif
diff --git a/hw/mcu/stm/stm32_common/src/hal_spi.c
b/hw/mcu/stm/stm32_common/src/hal_spi.c
index b4210d5a6..59b69c66f 100644
--- a/hw/mcu/stm/stm32_common/src/hal_spi.c
+++ b/hw/mcu/stm/stm32_common/src/hal_spi.c
@@ -505,7 +505,7 @@ stm32_spi_resolve_prescaler(uint8_t spi_num, uint32_t
baudrate, uint32_t *presca
* SPI ports from 0.
*/
switch (spi_num) {
-#if !MYNEWT_VAL(MCU_STM32F0)
+#if !MYNEWT_VAL(MCU_STM32F0) && !MYNEWT_VAL(MCU_STM32G0)
case 0:
case 3:
case 4:
@@ -666,7 +666,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings
*settings)
case 0:
__HAL_RCC_SPI1_CLK_ENABLE();
#if !MYNEWT_VAL(MCU_STM32F1)
- #if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0)
+ #if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0) &&
!MYNEWT_VAL(MCU_STM32G0)
gpio.Alternate = GPIO_AF5_SPI1;
#else
gpio.Alternate = GPIO_AF0_SPI1;
@@ -678,7 +678,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings
*settings)
case 1:
__HAL_RCC_SPI2_CLK_ENABLE();
#if !MYNEWT_VAL(MCU_STM32F1)
- #if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0)
+ #if !MYNEWT_VAL(MCU_STM32L0) && !MYNEWT_VAL(MCU_STM32F0) &&
!MYNEWT_VAL(MCU_STM32G0)
gpio.Alternate = GPIO_AF5_SPI2;
#else
gpio.Alternate = GPIO_AF0_SPI2;
@@ -689,7 +689,9 @@ hal_spi_config(int spi_num, struct hal_spi_settings
*settings)
#if SPI_2_ENABLED
case 2:
__HAL_RCC_SPI3_CLK_ENABLE();
-#if !MYNEWT_VAL(MCU_STM32F1)
+#if MYNEWT_VAL(MCU_STM32G0)
+ gpio.Alternate = GPIO_AF4_SPI3;
+#elif !MYNEWT_VAL(MCU_STM32F1)
gpio.Alternate = GPIO_AF6_SPI3;
#endif
break;
@@ -846,6 +848,9 @@ hal_spi_config(int spi_num, struct hal_spi_settings
*settings)
#ifdef SPI_NSS_PULSE_DISABLE
init->NSSPMode = SPI_NSS_PULSE_DISABLE;
#endif
+#ifdef SPI_MASTER_KEEP_IO_STATE_ENABLE
+ init->MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
+#endif
irq = stm32_resolve_spi_irq(&spi->handle);
NVIC_SetPriority(irq, cfg->irq_prio);
diff --git a/hw/mcu/stm/stm32_common/src/hal_uart.c
b/hw/mcu/stm/stm32_common/src/hal_uart.c
index 34d5e1397..4ad515109 100644
--- a/hw/mcu/stm/stm32_common/src/hal_uart.c
+++ b/hw/mcu/stm/stm32_common/src/hal_uart.c
@@ -132,9 +132,14 @@ static struct hal_uart_irq uart_irqs[4];
static struct hal_uart_irq uart_irqs[3];
#endif
+#if MYNEWT_VAL(MCU_STM32G0)
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
+#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
+#endif
+
#if !MYNEWT_VAL(STM32_HAL_UART_HAS_SR)
# define STATUS(x) ((x)->ISR)
-#if MYNEWT_VAL(MCU_STM32H7)
+#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32G0)
# define RXNE USART_ISR_RXNE_RXFNE
# define TXE USART_ISR_TXE_TXFNF
#else
@@ -144,7 +149,8 @@ static struct hal_uart_irq uart_irqs[3];
# define TC USART_ISR_TC
# define RXDR(x) ((x)->RDR)
# define TXDR(x) ((x)->TDR)
-#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) ||
MYNEWT_VAL(MCU_STM32U5)
+#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) ||
MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32G4) || \
+ MYNEWT_VAL(MCU_STM32G0)
# define BAUD(x,y) UART_DIV_SAMPLING16((x), (y), UART_PRESCALER_DIV1)
#else
# define BAUD(x,y) UART_DIV_SAMPLING16((x), (y))
@@ -557,7 +563,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t
databits, uint8_t stopbits,
#else
if (cfg->suc_uart == USART1) {
#endif
-#if MYNEWT_VAL(MCU_STM32F0)
+#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32G0)
u->u_regs->BRR = BAUD(HAL_RCC_GetPCLK1Freq(), baudrate);
#else
u->u_regs->BRR = BAUD(HAL_RCC_GetPCLK2Freq(), baudrate);
diff --git a/hw/mcu/stm/stm32_common/src/hal_watchdog.c
b/hw/mcu/stm/stm32_common/src/hal_watchdog.c
index 12159404a..421993fb4 100644
--- a/hw/mcu/stm/stm32_common/src/hal_watchdog.c
+++ b/hw/mcu/stm/stm32_common/src/hal_watchdog.c
@@ -52,6 +52,10 @@ hal_watchdog_init(uint32_t expire_msecs)
void
hal_watchdog_enable(void)
{
+ /* For F0, L0, G0, DBG clock needs to be enabled to enable watchdog freeze
in debug stop */
+#ifdef __HAL_RCC_DBGMCU_CLK_ENABLE
+ __HAL_RCC_DBGMCU_CLK_ENABLE();
+#endif
#if MYNEWT_VAL(MCU_STM32H7)
__HAL_DBGMCU_FREEZE_IWDG1();
#else
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/cmsis_nvic.h
b/hw/mcu/stm/stm32g0xx/include/mcu/cmsis_nvic.h
new file mode 100644
index 000000000..cd25c74c2
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/cmsis_nvic.h
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MCU_CMSIS_NVIC_H
+#define MCU_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_VECTOR_
+enum {
+//#include <mcu/mcu_vectors.h>
+ NVIC_VECTOR_COUNT = 31 + 16
+};
+#define NVIC_NUM_VECTORS (int)NVIC_VECTOR_COUNT
+
+#include <stm32g0xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/cortex_m0.h
b/hw/mcu/stm/stm32g0xx/include/mcu/cortex_m0.h
new file mode 100644
index 000000000..1ecf3c4f5
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/cortex_m0.h
@@ -0,0 +1,39 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_CORTEX_M0_H__
+#define __MCU_CORTEX_M0_H__
+
+#include "stm32g0xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+hal_debug_break(void)
+{
+ __BKPT(1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_CORTEX_M0_H__ */
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/mcu.h
b/hw/mcu/stm/stm32g0xx/include/mcu/mcu.h
new file mode 100644
index 000000000..3916bae1a
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/mcu.h
@@ -0,0 +1,38 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include <stm32g0xx.h>
+#include <stm32_common/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SVC_IRQ_NUMBER SVC_IRQn
+
+#define STM32_SYSTEM_MEMORY 0x0BF90000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_MCU_H_ */
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/mcu_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/mcu_vectors.h
new file mode 100644
index 000000000..8a66df7a5
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/mcu_vectors.h
@@ -0,0 +1,46 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#if defined(STM32G0B1xx)
+#include "vectors/stm32g0b1xx_vectors.h"
+#elif defined(STM32G0C1xx)
+#include "vectors/stm32g0c1xx_vectors.h"
+#elif defined(STM32G0B0xx)
+#include "vectors/stm32g0b0xx_vectors.h"
+#elif defined(STM32G071xx)
+#include "vectors/stm32g071xx_vectors.h"
+#elif defined(STM32G081xx)
+#include "vectors/stm32g081xx_vectors.h"
+#elif defined(STM32G070xx)
+#include "vectors/stm32g070xx_vectors.h"
+#elif defined(STM32G031xx)
+#include "vectors/stm32g031xx_vectors.h"
+#elif defined(STM32G041xx)
+#include "vectors/stm32g041xx_vectors.h"
+#elif defined(STM32G030xx)
+#include "vectors/stm32g030xx_vectors.h"
+#elif defined(STM32G051xx)
+#include "vectors/stm32g051xx_vectors.h"
+#elif defined(STM32G061xx)
+#include "vectors/stm32g061xx_vectors.h"
+#elif defined(STM32G050xx)
+#include "vectors/stm32g050xx_vectors.h"
+#else
+#error "Please select first the target STM32G0xx device used in your
application"
+#endif
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/stm32_hal.h
b/hw/mcu/stm/stm32g0xx/include/mcu/stm32_hal.h
new file mode 100644
index 000000000..fb84011e7
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/stm32_hal.h
@@ -0,0 +1,96 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef STM32_HAL_H
+#define STM32_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <mcu/cortex_m0.h>
+
+#include "stm32g0xx_hal.h"
+#include "stm32g0xx_hal_def.h"
+#include "stm32g0xx.h"
+#include "stm32g0xx_hal_dma.h"
+#include "stm32g0xx_hal_spi.h"
+#include "stm32g0xx_hal_gpio.h"
+#include "stm32g0xx_hal_gpio_ex.h"
+#include "stm32g0xx_hal_rcc.h"
+#include "stm32g0xx_hal_iwdg.h"
+#include "stm32g0xx_hal_i2c.h"
+#include "stm32g0xx_hal_uart.h"
+#include "mcu/stm32g0_bsp.h"
+#include "stm32g0xx_hal_tim.h"
+#include "stm32g0xx_ll_bus.h"
+#include "stm32g0xx_ll_tim.h"
+#include "stm32g0xx_hal_def.h"
+#include "stm32g0xx_hal_flash.h"
+#include "stm32g0xx_hal_flash_ex.h"
+#include "stm32g0xx_mynewt_hal.h"
+
+#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \
+ do { \
+ (x)->Init.Window = IWDG_WINDOW_DISABLE; \
+ } while (0)
+
+#define STM32_HAL_FLASH_REMAP()
+
+struct stm32_hal_spi_cfg {
+ int ss_pin; /* for slave mode */
+ int sck_pin;
+ int miso_pin;
+ int mosi_pin;
+ int irq_prio;
+};
+
+#define STM32_HAL_TIMER_MAX (3)
+
+/*
+ * Some TIMx interrupts are shared with other timer/peripheral
+ * Number here are used when interrupt name is different for
+ * variants of STM32G devices.
+ * i.e.:
+ * TIM3_IRQn = 16 for STM32G05
+ * TIM3_TIM4_IRQn = 16 for STM32G0B
+ */
+#define STM32_HAL_TIMER_TIM1_IRQ TIM1_CC_IRQn
+#define STM32_HAL_TIMER_TIM2_IRQ TIM2_IRQn
+#define STM32_HAL_TIMER_TIM3_IRQ 16
+#define STM32_HAL_TIMER_TIM4_IRQ 16
+#define STM32_HAL_TIMER_TIM6_IRQ 17
+#define STM32_HAL_TIMER_TIM7_IRQ 18
+#define STM32_HAL_TIMER_TIM14_IRQ TIM14_IRQn
+#define STM32_HAL_TIMER_TIM15_IRQ TIM15_IRQn
+#define STM32_HAL_TIMER_TIM16_IRQ 21
+#define STM32_HAL_TIMER_TIM17_IRQ 22
+
+#define STM32_HAL_FLASH_INIT() \
+ do { \
+ HAL_FLASH_Unlock(); \
+ } while (0)
+#define FLASH_PROGRAM_TYPE FLASH_TYPEPROGRAM_DOUBLEWORD
+#define STM32_HAL_FLASH_CLEAR_ERRORS()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_H */
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0_bsp.h
b/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0_bsp.h
new file mode 100644
index 000000000..c1649dd0a
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0_bsp.h
@@ -0,0 +1,57 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32G0_BSP_H_
+#define __MCU_STM32G0_BSP_H_
+
+#include <hal/hal_gpio.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * BSP specific UART settings.
+ */
+struct stm32_uart_cfg {
+ USART_TypeDef *suc_uart; /* UART dev registers */
+ volatile uint32_t *suc_rcc_reg; /* RCC register to modify */
+ uint32_t suc_rcc_dev; /* RCC device ID */
+ int8_t suc_pin_tx; /* pins for IO */
+ int8_t suc_pin_rx;
+ int8_t suc_pin_rts;
+ int8_t suc_pin_cts;
+ uint8_t suc_pin_af; /* AF selection for this */
+ IRQn_Type suc_irqn; /* NVIC IRQn */
+};
+
+/*
+ * Internal API for stm32g0xx mcu specific code.
+ */
+int hal_gpio_init_af(int pin, uint8_t af_type, enum hal_gpio_pull pull,
uint8_t od);
+
+struct hal_flash;
+extern struct hal_flash stm32g0_flash_dev;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32G0_BSP_H_ */
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0xx_mynewt_hal.h
b/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0xx_mynewt_hal.h
new file mode 100644
index 000000000..41b87fb27
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/stm32g0xx_mynewt_hal.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32G0_MYNEWT_HAL_H
+#define __MCU_STM32G0_MYNEWT_HAL_H
+
+#include "stm32g0xx.h"
+#include "stm32g0xx_hal_dma.h"
+#include "stm32g0xx_hal_gpio.h"
+#include "stm32g0xx_hal_i2c.h"
+#include "stm32g0xx_hal_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while(0);
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while(0);
+
+
+int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg);
+int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg);
+
+struct stm32_hal_i2c_cfg {
+ I2C_TypeDef *hic_i2c;
+ volatile uint32_t *hic_rcc_reg; /* RCC register to modify */
+ uint32_t hic_rcc_dev; /* RCC device ID */
+ uint8_t hic_pin_sda;
+ uint8_t hic_pin_scl;
+ uint8_t hic_pin_af;
+ uint8_t hic_10bit;
+ uint32_t hic_timingr; /* TIMINGR register */
+ uint32_t hic_speed; /* Requested speed (used when
hic_timingr is 0) */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32G0_MYNEWT_HAL_H */
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g030xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g030xx_vectors.h
new file mode 100644
index 000000000..2336577a1
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g030xx_vectors.h
@@ -0,0 +1,65 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR_UNUSED(0)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g031xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g031xx_vectors.h
new file mode 100644
index 000000000..4c98dda23
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g031xx_vectors.h
@@ -0,0 +1,66 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR_UNUSED(0)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g041xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g041xx_vectors.h
new file mode 100644
index 000000000..ecdab4aff
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g041xx_vectors.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(AES_RNG_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g050xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g050xx_vectors.h
new file mode 100644
index 000000000..a7ac7aa87
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g050xx_vectors.h
@@ -0,0 +1,64 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g051xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g051xx_vectors.h
new file mode 100644
index 000000000..786206da0
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g051xx_vectors.h
@@ -0,0 +1,65 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g061xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g061xx_vectors.h
new file mode 100644
index 000000000..d0a980e75
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g061xx_vectors.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(AES_RNG_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g070xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g070xx_vectors.h
new file mode 100644
index 000000000..698eb9b5c
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g070xx_vectors.h
@@ -0,0 +1,65 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_4_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g071xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g071xx_vectors.h
new file mode 100644
index 000000000..fc77fab7e
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g071xx_vectors.h
@@ -0,0 +1,66 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR(UCPD1_2_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_4_LPUART1_IRQHandler)
+INT_VECTOR(CEC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g081xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g081xx_vectors.h
new file mode 100644
index 000000000..ced3436c0
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g081xx_vectors.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR(UCPD1_2_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_4_LPUART1_IRQHandler)
+INT_VECTOR(CEC_IRQHandler)
+INT_VECTOR(AES_RNG_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b0xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b0xx_vectors.h
new file mode 100644
index 000000000..24dc1c9f9
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b0xx_vectors.h
@@ -0,0 +1,65 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR(USB_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM3_TIM4_IRQHandler)
+INT_VECTOR(TIM6_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_IRQHandler)
+INT_VECTOR(TIM17_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_3_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_3_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_4_5_6_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b1xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b1xx_vectors.h
new file mode 100644
index 000000000..468e756bc
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0b1xx_vectors.h
@@ -0,0 +1,66 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_VDDIO2_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_CRS_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR(USB_UCPD1_2_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_TIM4_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_FDCAN_IT0_IRQHandler)
+INT_VECTOR(TIM17_FDCAN_IT1_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_3_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_3_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_LPUART2_IRQHandler)
+INT_VECTOR(USART3_4_5_6_LPUART1_IRQHandler)
+INT_VECTOR(CEC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0c1xx_vectors.h
b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0c1xx_vectors.h
new file mode 100644
index 000000000..5b062dd48
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/include/mcu/vectors/stm32g0c1xx_vectors.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_VDDIO2_IRQHandler)
+INT_VECTOR(RTC_TAMP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_CRS_IRQHandler)
+INT_VECTOR(EXTI0_1_IRQHandler)
+INT_VECTOR(EXTI2_3_IRQHandler)
+INT_VECTOR(EXTI4_15_IRQHandler)
+INT_VECTOR(USB_UCPD1_2_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_3_IRQHandler)
+INT_VECTOR(DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler)
+INT_VECTOR(ADC1_COMP_IRQHandler)
+INT_VECTOR(TIM1_BRK_UP_TRG_COM_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_TIM4_IRQHandler)
+INT_VECTOR(TIM6_DAC_LPTIM1_IRQHandler)
+INT_VECTOR(TIM7_LPTIM2_IRQHandler)
+INT_VECTOR(TIM14_IRQHandler)
+INT_VECTOR(TIM15_IRQHandler)
+INT_VECTOR(TIM16_FDCAN_IT0_IRQHandler)
+INT_VECTOR(TIM17_FDCAN_IT1_IRQHandler)
+INT_VECTOR(I2C1_IRQHandler)
+INT_VECTOR(I2C2_3_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_3_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_LPUART2_IRQHandler)
+INT_VECTOR(USART3_4_5_6_LPUART1_IRQHandler)
+INT_VECTOR(CEC_IRQHandler)
+INT_VECTOR(AES_RNG_IRQHandler)
diff --git a/hw/mcu/stm/stm32g0xx/pkg.yml b/hw/mcu/stm/stm32g0xx/pkg.yml
new file mode 100644
index 000000000..d25713a82
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/pkg.yml
@@ -0,0 +1,65 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/stm/stm32g0xx
+pkg.description: MCU definition for STM32G0 ARM Cortex-M0+ chips.
+pkg.author: "Apache Mynewt <d...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/";
+pkg.keywords:
+ - stm32
+ - stm32g0
+
+pkg.type: sdk
+
+pkg.ign_files:
+ - ".*template.*"
+
+pkg.include_dirs:
+ - "@stm-cmsis_device_g0/Include"
+ - "@stm-stm32g0xx_hal_driver/Inc"
+
+pkg.src_dirs:
+ - "@stm-stm32g0xx_hal_driver/Src"
+ - "src"
+
+pkg.ign_dirs:
+ - "Device"
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/boot/startup"
+
+pkg.deps.'(SPI_0_MASTER || SPI_1_MASTER || SPI_2_MASTER) &&
BUS_DRIVER_PRESENT':
+ - "@apache-mynewt-core/hw/bus/drivers/spi_stm32"
+
+repository.stm-cmsis_device_g0:
+ type: github
+ vers: v1.4.3-commit
+ branch: master
+ user: STMicroelectronics
+ repo: cmsis_device_g0
+
+repository.stm-stm32g0xx_hal_driver:
+ type: github
+ vers: v1.4.5-commit
+ branch: master
+ user: STMicroelectronics
+ repo: stm32g0xx_hal_driver
diff --git a/hw/mcu/stm/stm32g0xx/src/clock_stm32g0xx.c
b/hw/mcu/stm/stm32g0xx/src/clock_stm32g0xx.c
new file mode 100644
index 000000000..571483947
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/clock_stm32g0xx.c
@@ -0,0 +1,251 @@
+/*
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without
modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
notice,
+ * this list of conditions and the following disclaimer in the
documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its
contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stm32g0xx_hal_pwr_ex.h>
+#include <stm32g0xx_hal_rcc.h>
+#include <stm32g0xx_hal.h>
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__)
== RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__)
== RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__)
== RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) ||
((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) ==
RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) ==
RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+/*
+ * This allows an user to have a custom clock configuration by zeroing
+ * every possible clock source in the syscfg.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE) || \
+ MYNEWT_VAL(STM32_CLOCK_LSE) || MYNEWT_VAL(STM32_CLOCK_HSI) || \
+ MYNEWT_VAL(STM32_CLOCK_HSI48) || MYNEWT_VAL(STM32_CLOCK_LSI)
+
+#define TRNG_ENABLED (MYNEWT_VAL(TRNG) != 0)
+
+_Static_assert(MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_HSI),
+ "HSI and/or HSE must be enabled");
+
+void
+SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef osc_init = {};
+ RCC_ClkInitTypeDef clk_init = {};
+ HAL_StatusTypeDef status;
+#if TRNG_ENABLED
+ RCC_PeriphCLKInitTypeDef pclk_init;
+#endif
+
+ /*
+ * The voltage scaling allows optimizing the power consumption when the
+ * device is clocked below the maximum system frequency, to update the
+ * voltage scaling value regarding system frequency refer to product
+ * datasheet.
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
HAL_PWREx_ControlVoltageScaling(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG));
+
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+
+ /*
+ * LSI is used to clock the independent watchdog and optionally the RTC.
+ * It can be disabled per user request, but will be automatically enabled
+ * again when the IWDG is started.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
+ if (MYNEWT_VAL(STM32_CLOCK_LSI)) {
+ osc_init.LSIState = RCC_LSI_ON;
+ } else {
+ osc_init.LSIState = RCC_LSI_OFF;
+ }
+
+ /*
+ * LSE is only used to clock the RTC.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
+ if (MYNEWT_VAL(STM32_CLOCK_LSE)) {
+ if (MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS)) {
+ osc_init.LSEState = RCC_LSE_BYPASS;
+ } else {
+ osc_init.LSEState = RCC_LSE_ON;
+ }
+ } else {
+ osc_init.LSEState = RCC_LSE_OFF;
+ }
+
+ /*
+ * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source)
+ */
+ if (MYNEWT_VAL(STM32_CLOCK_HSE)) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+
+ if (MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS)) {
+ osc_init.HSEState = RCC_HSE_BYPASS;
+ } else {
+ osc_init.HSEState = RCC_HSE_ON;
+ }
+ }
+
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSI) ||
MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION) <= 127,
+ "Invalid HSI calibration value");
+ /*
+ * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is
+ * already turned on by default but a new calibration setting might be
+ * used. If the user chooses to turn it off, it must be turned off after
+ * SYSCLK was updated to use HSE/PLL.
+ */
+ if (MYNEWT_VAL(STM32_CLOCK_HSI)) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_ON;
+ /* HSI calibration is not optional when HSI is enabled */
+ osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION);
+ }
+
+ /*
+ * HSI48 can be used to drive USB/RNG
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+ if (MYNEWT_VAL(STM32_CLOCK_HSI48)) {
+ osc_init.HSI48State = RCC_HSI48_ON;
+ } else {
+ osc_init.HSI48State = RCC_HSI48_OFF;
+ }
+
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)),
+ "PLLM value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)),
+ "PLLN value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)),
+ "PLLP value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)),
+ "PLLQ value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)),
+ "PLLR value is invalid");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_PLL) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, PLL_R),
+ "PLL selected as system clock but not enabled");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSE) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSE),
+ "HSE selected as system clock but not enabled");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSI) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSI),
+ "HSI selected as system clock but not enabled");
+
+ if (MYNEWT_VAL(STM32_CLOCK_PLL)) {
+ /*
+ * Default to MSI, HSE or HSI48 as PLL source when multiple high-speed
+ * sources are enabled.
+ */
+ osc_init.PLL.PLLState = RCC_PLL_ON;
+ if (MYNEWT_VAL(STM32_CLOCK_HSE)) {
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ } else {
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ }
+
+ osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM);
+ osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN);
+ osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP);
+ osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ);
+ osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR);
+ }
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1;
+ if (MYNEWT_VAL(STM32_CLOCK_PLL) &&
+ (MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, PLL_R) ||
MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, auto))) {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ } else if (MYNEWT_VAL(STM32_CLOCK_HSE) &&
+ (MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSE) ||
+ MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, auto))) {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+ } else {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ }
+
+ _Static_assert(IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER)), "AHB
clock divider is invalid");
+ _Static_assert(IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER)), "APB1
clock divider is invalid");
+ _Static_assert(IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER)), "APB2
clock divider is invalid");
+
+ clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER);
+ clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER);
+
+ _Static_assert(IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY)), "Flash
latency value is invalid");
+
+ status = HAL_RCC_ClockConfig(&clk_init, MYNEWT_VAL(STM32_FLASH_LATENCY));
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ if ((MYNEWT_VAL(STM32_CLOCK_HSI) == 0) || (MYNEWT_VAL(STM32_CLOCK_HSE) ==
0)) {
+ /*
+ * Turn off HSE/HSI oscillator; this must be done at the end because
+ * SYSCLK source has to be updated first.
+ */
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+ if (MYNEWT_VAL(STM32_CLOCK_HSE) == 0) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+ osc_init.HSEState = RCC_HSE_OFF;
+ }
+ if (MYNEWT_VAL(STM32_CLOCK_HSI) == 0) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_OFF;
+ }
+ }
+
+ osc_init.PLL.PLLState = RCC_PLL_NONE;
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+#if TRNG_ENABLED
+ pclk_init.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+ /* Other clock sources are possible, but since right now we always
+ * configure the PLL, this should be ok
+ */
+ pclk_init.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
+ status = HAL_RCCEx_PeriphCLKConfig(&pclk_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+#endif
+
+ if (PREFETCH_ENABLE) {
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ }
+
+ if (MYNEWT_VAL(STM32_ENABLE_ICACHE)) {
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+}
+#endif
diff --git a/hw/mcu/stm/stm32g0xx/src/hal_flash.c
b/hw/mcu/stm/stm32g0xx/src/hal_flash.c
new file mode 100644
index 000000000..69b8b7ee6
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/hal_flash.c
@@ -0,0 +1,56 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <syscfg/syscfg.h>
+#include <mcu/stm32_hal.h>
+#include "hal/hal_flash_int.h"
+
+#define STM32_FLASH_SIZE (MYNEWT_VAL(STM32_FLASH_SIZE_KB) * 1024)
+
+int
+stm32_mcu_flash_erase_sector(const struct hal_flash *dev, uint32_t
sector_address)
+{
+ FLASH_EraseInitTypeDef eraseinit;
+ uint32_t PageError;
+ HAL_StatusTypeDef rc;
+
+ (void)PageError;
+
+ if (!(sector_address & (FLASH_PAGE_SIZE - 1))) {
+ eraseinit.TypeErase = FLASH_TYPEERASE_PAGES;
+#ifdef FLASH_BANK_2
+ if ((sector_address - dev->hf_base_addr) < (STM32_FLASH_SIZE / 2)) {
+ eraseinit.Banks = FLASH_BANK_1;
+ }
+ else {
+ eraseinit.Banks = FLASH_BANK_2;
+ }
+#else
+ eraseinit.Banks = FLASH_BANK_1;
+#endif
+ eraseinit.Page = (sector_address - dev->hf_base_addr) /
FLASH_PAGE_SIZE;
+ eraseinit.NbPages = 1;
+ rc = HAL_FLASHEx_Erase(&eraseinit, &PageError);
+ if (rc == HAL_OK) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
diff --git a/hw/mcu/stm/stm32g0xx/src/hal_reset_cause.c
b/hw/mcu/stm/stm32g0xx/src/hal_reset_cause.c
new file mode 100644
index 000000000..16fc3e0a2
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/hal_reset_cause.c
@@ -0,0 +1,46 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <hal/hal_system.h>
+
+#include "stm32g0xx_hal_def.h"
+
+enum hal_reset_reason
+hal_reset_cause(void)
+{
+ static enum hal_reset_reason reason;
+ uint32_t reg;
+
+ if (reason) {
+ return reason;
+ }
+
+ reg = RCC->CSR;
+
+ if (reg & (RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF)) {
+ reason = HAL_RESET_WATCHDOG;
+ } else if (reg & RCC_CSR_SFTRSTF) {
+ reason = HAL_RESET_SOFT;
+ } else if (reg & RCC_CSR_PINRSTF) {
+ reason = HAL_RESET_PIN;
+ } else {
+ reason = HAL_RESET_POR;
+ }
+ RCC->CSR |= RCC_CSR_RMVF;
+ return reason;
+}
diff --git a/hw/mcu/stm/stm32g0xx/src/hal_system_init.c
b/hw/mcu/stm/stm32g0xx/src/hal_system_init.c
new file mode 100644
index 000000000..dc995be19
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/hal_system_init.c
@@ -0,0 +1,53 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/mynewt.h"
+#include "mcu/stm32_hal.h"
+#include <hal/hal_system.h>
+
+extern char __vector_tbl_reloc__[];
+
+/*
+ * XXX BSP specific
+ */
+void SystemClock_Config(void);
+
+void
+hal_system_init(void)
+{
+ SCB->VTOR = (uint32_t)&__vector_tbl_reloc__;
+
+ /* Configure System Clock */
+ SystemClock_Config();
+
+ /* Update SystemCoreClock global variable */
+ SystemCoreClockUpdate();
+
+ /* Relocate the vector table */
+ NVIC_Relocate();
+
+ if (PREFETCH_ENABLE) {
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ }
+
+ if (MYNEWT_VAL(STM32_ENABLE_ICACHE)) {
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+}
+
diff --git a/hw/mcu/stm/stm32g0xx/src/hal_timer_freq.c
b/hw/mcu/stm/stm32g0xx/src/hal_timer_freq.c
new file mode 100644
index 000000000..c23db9137
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/hal_timer_freq.c
@@ -0,0 +1,84 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <inttypes.h>
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <hal/hal_timer.h>
+#include "mcu/stm32_hal.h"
+#include "stm32_common/stm32_hal.h"
+
+
+/*
+ * Generic implementation for determining the frequency
+ * of a timer.
+ */
+
+uint32_t
+stm32_hal_timer_get_freq(void *regs)
+{
+ RCC_ClkInitTypeDef clocks;
+ uint32_t fl;
+ uint32_t freq;
+
+ HAL_RCC_GetClockConfig(&clocks, &fl);
+
+ switch ((uintptr_t)regs) {
+#ifdef TIM1
+ case (uintptr_t)TIM1:
+#endif
+#ifdef TIM2
+ case (uintptr_t)TIM2:
+#endif
+#ifdef TIM3
+ case (uintptr_t)TIM3:
+#endif
+#ifdef TIM4
+ case (uintptr_t)TIM4:
+#endif
+#ifdef TIM6
+ case (uintptr_t)TIM6:
+#endif
+#ifdef TIM7
+ case (uintptr_t)TIM7:
+#endif
+#ifdef TIM14
+ case (uintptr_t)TIM14:
+#endif
+#ifdef TIM15
+ case (uintptr_t)TIM15:
+#endif
+#ifdef TIM16
+ case (uintptr_t)TIM16:
+#endif
+#ifdef TIM17
+ case (uintptr_t)TIM17:
+#endif
+ freq = HAL_RCC_GetPCLK1Freq();
+ if (clocks.APB1CLKDivider) {
+ freq *= 2;
+ }
+ break;
+ default:
+ return 0;
+ }
+ return freq;
+}
diff --git a/hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c
b/hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c
new file mode 100644
index 000000000..1975f6d0b
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c
@@ -0,0 +1,306 @@
+/**
+
******************************************************************************
+ * @file system_stm32g0xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called
from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset
and
+ * before branch to main program. This call is made
inside
+ * the "startup_stm32g0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be
used
+ * by the user application to setup the
SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and
must
+ * be called whenever the core clock is
changed
+ * during program execution.
+ *
+ * After each device reset the HSI (8 MHz then 16 MHz) is used as system
clock source.
+ * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+
*=============================================================================
+
*-----------------------------------------------------------------------------
+ * System Clock source | HSI
+
*-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 16000000
+
*-----------------------------------------------------------------------------
+ * HCLK(Hz) | 16000000
+
*-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+
*-----------------------------------------------------------------------------
+ * APB Prescaler | 1
+
*-----------------------------------------------------------------------------
+ * HSI Division factor | 1
+
*-----------------------------------------------------------------------------
+ * PLL_M | 1
+
*-----------------------------------------------------------------------------
+ * PLL_N | 8
+
*-----------------------------------------------------------------------------
+ * PLL_P | 7
+
*-----------------------------------------------------------------------------
+ * PLL_Q | 2
+
*-----------------------------------------------------------------------------
+ * PLL_R | 2
+
*-----------------------------------------------------------------------------
+ * Require 48MHz for RNG | Disabled
+
*-----------------------------------------------------------------------------
+
*=============================================================================
+
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32g0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32G0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32g0xx.h"
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in
Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in
Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */
+
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration
************************/
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address
field.
+ This value must be a
multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset
field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address
field.
+ This value must be a
multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset
field.
+ This value must be a
multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system
clock frequency
+ Note: If you use this function to configure the system clock; then
there
+ is no need to call the 2 first functions listed above, since
SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 16000000UL;
+
+ const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL,
0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
+ const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL,
4UL};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* Configure the Vector Table location
-------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table
Relocation */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be
called
+ * to update SystemCoreClock variable value. Otherwise, any
configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
HSI_VALUE(**) / HSI division factor
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
HSE_VALUE(***)
+ *
+ * - If SYSCLK source is LSI, SystemCoreClock will contain the
LSI_VALUE
+ *
+ * - If SYSCLK source is LSE, SystemCoreClock will contain the
LSE_VALUE
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
HSE_VALUE(***)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file
(default value
+ * 16 MHz) but the real value may vary depending on the
variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file
(default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using
fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp;
+ uint32_t pllvco;
+ uint32_t pllr;
+ uint32_t pllsource;
+ uint32_t pllm;
+ uint32_t hsidiv;
+
+ /* Get SYSCLK source
-------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_0: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
+ SystemCoreClock = LSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_2: /* LSE used as system clock */
+ SystemCoreClock = LSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_1: /* PLL used as system clock */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
+
+ if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+ {
+ pllvco = (HSE_VALUE / pllm);
+ }
+ else /* HSI used as PLL clock source */
+ {
+ pllvco = (HSI_VALUE / pllm);
+ }
+ pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >>
RCC_PLLCFGR_PLLN_Pos);
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) +
1UL);
+
+ SystemCoreClock = pllvco/pllr;
+ break;
+
+ case 0x00000000U: /* HSI used as system clock */
+ default: /* HSI used as system clock */
+ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>>
RCC_CR_HSIDIV_Pos));
+ SystemCoreClock = (HSI_VALUE/hsidiv);
+ break;
+ }
+ /* Compute HCLK clock frequency
--------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/hw/mcu/stm/stm32g0xx/syscfg.yml b/hw/mcu/stm/stm32g0xx/syscfg.yml
new file mode 100644
index 000000000..7109837d0
--- /dev/null
+++ b/hw/mcu/stm/stm32g0xx/syscfg.yml
@@ -0,0 +1,149 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 8
+
+ MCU_STM32G0:
+ description: MCUs are of STM32G0xx family
+ value: 1
+
+ STM32_CLOCK_VOLTAGESCALING_CONFIG:
+ description: >
+ Adjust voltage scaling.
+ PWR_REGULATOR_VOLTAGE_SCALE1_BOOST for system clock > 150MHz
+ PWR_REGULATOR_VOLTAGE_SCALE1 for system clock up to 150MHz
+ PWR_REGULATOR_VOLTAGE_SCALE2 for system clock <= 26MHz
+ value: PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
+
+ STM32_CLOCK_LSI:
+ description: Enable low-speed internal clock source
+ value: 0
+
+ STM32_CLOCK_LSE:
+ description: Enable low-speed external clock source (aka RTC xtal)
+ value: 0
+
+ STM32_CLOCK_LSE_BYPASS:
+ description: 0 for 32768 xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSE:
+ description: Enable high-speed external clock source
+ value: 0
+
+ STM32_CLOCK_HSE_BYPASS:
+ description: 0 for xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSI:
+ description: Enable high-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_HSI_CALIBRATION:
+ description: HSI calibration value
+ value: 'RCC_HSICALIBRATION_DEFAULT'
+
+ STM32_CLOCK_HSI48:
+ description: Enable high-speed 48MHz internal clock source
+ value: 0
+
+ STM32_CLOCK_SYSCLK:
+ description: Select SYSCLK source
+ choices:
+ - HSI
+ - HSE
+ - PLL_R
+ - auto
+ value: auto
+
+ STM32_CLOCK_PLL:
+ description: Enable PLL
+ value: 0
+
+ STM32_CLOCK_PLL_PLLM:
+ description: PLL config M parameter
+ value: 4
+
+ STM32_CLOCK_PLL_PLLN:
+ description: PLL config N parameter
+ value: 85
+
+ STM32_CLOCK_PLL_PLLP:
+ description: PLL config P parameter
+ value: 2
+
+ STM32_CLOCK_PLL_PLLQ:
+ description: PLL config Q parameter
+ value: 2
+
+ STM32_CLOCK_PLL_PLLR:
+ description: PLL config R parameter
+ value: 2
+
+ STM32_CLOCK_AHB_DIVIDER:
+ description: AHB CLK1 prescaler
+ value: RCC_SYSCLK_DIV1
+
+ STM32_CLOCK_APB1_DIVIDER:
+ description: APB1 prescaler
+ value: RCC_HCLK_DIV1
+
+ STM32_CLOCK_APB2_DIVIDER:
+ description: APB2 prescaler
+ value: RCC_HCLK_DIV1
+
+ STM32_FLASH_LATENCY:
+ description: Number of wait-states
+ value: FLASH_LATENCY_2
+
+ STM32_ENABLE_ICACHE:
+ description: Enable instruction caching
+ value: 1
+
+ STM32_ENABLE_DCACHE:
+ description: Enable instruction caching
+ value: 1
+
+ STM32_FLASH_PREFETCH_ENABLE:
+ description: Enable pre-fetch of instructions (when latency > 0)
+ value: 1
+
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI with FIFO
+ value: 1
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has no clock speed register (has TIMINGR)
+ value: 0
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses ISR register (not SR) for status.
+ value: 0
+
+ MCU_FLASH_ERASED_VAL:
+ description: Value read from erased flash.
+ value: 0xff
+
+syscfg.vals:
+ MCU_RAM_START: 0x20000000
+ MCU_RAM_SIZE: 0x1C000
