This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 1b3d4c61549ed835bd506c85ae7e645a2877b9b9
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Mon Dec 4 08:19:54 2023 +0100
mcu/stm32: Add STM32G4 MCU files
This adds support for STM32G4 MCU family.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
---
hw/bus/drivers/spi_stm32/pkg.yml | 3 +
.../spi_stm32/stm32g4xx/include/spidmacfg.h | 159 +++++++++++
hw/bus/drivers/spi_stm32/{ => stm32g4xx}/pkg.yml | 40 +--
hw/bus/drivers/spi_stm32/stm32g4xx/src/spidmacfg.c | 182 +++++++++++++
hw/bus/drivers/spi_stm32/stm32g4xx/syscfg.yml | 66 +++++
hw/mcu/stm/stm32g4xx/include/mcu/cmsis_nvic.h | 33 +++
hw/mcu/stm/stm32g4xx/include/mcu/cortex_m4.h | 39 +++
hw/mcu/stm/stm32g4xx/include/mcu/mcu.h | 38 +++
hw/mcu/stm/stm32g4xx/include/mcu/mcu_vectors.h | 42 +++
hw/mcu/stm/stm32g4xx/include/mcu/stm32_hal.h | 81 ++++++
hw/mcu/stm/stm32g4xx/include/mcu/stm32g4_bsp.h | 57 ++++
.../stm32g4xx/include/mcu/stm32g4xx_mynewt_hal.h | 67 +++++
.../include/mcu/vectors/stm32g431xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g441xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g471xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g473xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g474xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g483xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g484xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g491xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32g4a1xx_vectors.h | 137 ++++++++++
.../include/mcu/vectors/stm32gbk1cb_vectors.h | 137 ++++++++++
hw/mcu/stm/stm32g4xx/pkg.yml | 65 +++++
hw/mcu/stm/stm32g4xx/src/clock_stm32g4xx.c | 244 +++++++++++++++++
hw/mcu/stm/stm32g4xx/src/hal_flash.c | 56 ++++
hw/mcu/stm/stm32g4xx/src/hal_reset_cause.c | 48 ++++
hw/mcu/stm/stm32g4xx/src/hal_system_init.c | 43 +++
hw/mcu/stm/stm32g4xx/src/hal_timer_freq.c | 96 +++++++
hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c | 297 +++++++++++++++++++++
hw/mcu/stm/stm32g4xx/stm32g4xx.ld | 209 +++++++++++++++
hw/mcu/stm/stm32g4xx/syscfg.yml | 149 +++++++++++
31 files changed, 3347 insertions(+), 37 deletions(-)
diff --git a/hw/bus/drivers/spi_stm32/pkg.yml b/hw/bus/drivers/spi_stm32/pkg.yml
index b1cfb709c..890359db8 100644
--- a/hw/bus/drivers/spi_stm32/pkg.yml
+++ b/hw/bus/drivers/spi_stm32/pkg.yml
@@ -42,6 +42,9 @@ pkg.deps.MCU_STM32F4:
pkg.deps.MCU_STM32F7:
- hw/bus/drivers/spi_stm32/stm32f7xx
+pkg.deps.MCU_STM32G4:
+ - hw/bus/drivers/spi_stm32/stm32g4xx
+
pkg.deps.MCU_STM32L0:
- hw/bus/drivers/spi_stm32/stm32l0xx
diff --git a/hw/bus/drivers/spi_stm32/stm32g4xx/include/spidmacfg.h
b/hw/bus/drivers/spi_stm32/stm32g4xx/include/spidmacfg.h
new file mode 100644
index 000000000..fba86aa71
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g4xx/include/spidmacfg.h
@@ -0,0 +1,159 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stm32g4xx_hal_dma.h>
+
+struct stm32_dma_cfg {
+ uint8_t dma_ch;
+ uint8_t irqn;
+ void (*irq_handler)(void);
+ DMA_Channel_TypeDef *regs;
+ DMA_InitTypeDef init;
+};
+
+#define SPI_DMA_RX_CHANNEL(dma, ch, spi_num) \
+ extern const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ##
spi_num ## _rx;
+
+#define SPI_DMA_TX_CHANNEL(dma, ch, spi_num) \
+ extern const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ##
spi_num ## _tx;
+
+SPI_DMA_RX_CHANNEL(1, 1, 1);
+SPI_DMA_RX_CHANNEL(1, 2, 1);
+SPI_DMA_RX_CHANNEL(1, 3, 1);
+SPI_DMA_RX_CHANNEL(1, 4, 1);
+SPI_DMA_RX_CHANNEL(1, 5, 1);
+SPI_DMA_RX_CHANNEL(1, 6, 1);
+SPI_DMA_RX_CHANNEL(1, 7, 1);
+SPI_DMA_RX_CHANNEL(2, 1, 1);
+SPI_DMA_RX_CHANNEL(2, 2, 1);
+SPI_DMA_RX_CHANNEL(2, 3, 1);
+SPI_DMA_RX_CHANNEL(2, 4, 1);
+SPI_DMA_RX_CHANNEL(2, 5, 1);
+SPI_DMA_RX_CHANNEL(2, 6, 1);
+SPI_DMA_RX_CHANNEL(2, 7, 1);
+
+SPI_DMA_RX_CHANNEL(1, 1, 2);
+SPI_DMA_RX_CHANNEL(1, 2, 2);
+SPI_DMA_RX_CHANNEL(1, 3, 2);
+SPI_DMA_RX_CHANNEL(1, 4, 2);
+SPI_DMA_RX_CHANNEL(1, 5, 2);
+SPI_DMA_RX_CHANNEL(1, 6, 2);
+SPI_DMA_RX_CHANNEL(1, 7, 2);
+SPI_DMA_RX_CHANNEL(2, 1, 2);
+SPI_DMA_RX_CHANNEL(2, 2, 2);
+SPI_DMA_RX_CHANNEL(2, 3, 2);
+SPI_DMA_RX_CHANNEL(2, 4, 2);
+SPI_DMA_RX_CHANNEL(2, 5, 2);
+SPI_DMA_RX_CHANNEL(2, 6, 2);
+SPI_DMA_RX_CHANNEL(2, 7, 2);
+
+SPI_DMA_RX_CHANNEL(1, 1, 3);
+SPI_DMA_RX_CHANNEL(1, 2, 3);
+SPI_DMA_RX_CHANNEL(1, 3, 3);
+SPI_DMA_RX_CHANNEL(1, 4, 3);
+SPI_DMA_RX_CHANNEL(1, 5, 3);
+SPI_DMA_RX_CHANNEL(1, 6, 3);
+SPI_DMA_RX_CHANNEL(1, 7, 3);
+SPI_DMA_RX_CHANNEL(2, 1, 3);
+SPI_DMA_RX_CHANNEL(2, 2, 3);
+SPI_DMA_RX_CHANNEL(2, 3, 3);
+SPI_DMA_RX_CHANNEL(2, 4, 3);
+SPI_DMA_RX_CHANNEL(2, 5, 3);
+SPI_DMA_RX_CHANNEL(2, 6, 3);
+SPI_DMA_RX_CHANNEL(2, 7, 3);
+
+#if defined(SPI4)
+SPI_DMA_RX_CHANNEL(1, 1, 4);
+SPI_DMA_RX_CHANNEL(1, 2, 4);
+SPI_DMA_RX_CHANNEL(1, 3, 4);
+SPI_DMA_RX_CHANNEL(1, 4, 4);
+SPI_DMA_RX_CHANNEL(1, 5, 4);
+SPI_DMA_RX_CHANNEL(1, 6, 4);
+SPI_DMA_RX_CHANNEL(1, 7, 4);
+SPI_DMA_RX_CHANNEL(2, 1, 4);
+SPI_DMA_RX_CHANNEL(2, 2, 4);
+SPI_DMA_RX_CHANNEL(2, 3, 4);
+SPI_DMA_RX_CHANNEL(2, 4, 4);
+SPI_DMA_RX_CHANNEL(2, 5, 4);
+SPI_DMA_RX_CHANNEL(2, 6, 4);
+SPI_DMA_RX_CHANNEL(2, 7, 4);
+#endif
+
+SPI_DMA_TX_CHANNEL(1, 1, 1);
+SPI_DMA_TX_CHANNEL(1, 2, 1);
+SPI_DMA_TX_CHANNEL(1, 3, 1);
+SPI_DMA_TX_CHANNEL(1, 4, 1);
+SPI_DMA_TX_CHANNEL(1, 5, 1);
+SPI_DMA_TX_CHANNEL(1, 6, 1);
+SPI_DMA_TX_CHANNEL(1, 7, 1);
+SPI_DMA_TX_CHANNEL(2, 1, 1);
+SPI_DMA_TX_CHANNEL(2, 2, 1);
+SPI_DMA_TX_CHANNEL(2, 3, 1);
+SPI_DMA_TX_CHANNEL(2, 4, 1);
+SPI_DMA_TX_CHANNEL(2, 5, 1);
+SPI_DMA_TX_CHANNEL(2, 6, 1);
+SPI_DMA_TX_CHANNEL(2, 7, 1);
+
+SPI_DMA_TX_CHANNEL(1, 1, 2);
+SPI_DMA_TX_CHANNEL(1, 2, 2);
+SPI_DMA_TX_CHANNEL(1, 3, 2);
+SPI_DMA_TX_CHANNEL(1, 4, 2);
+SPI_DMA_TX_CHANNEL(1, 5, 2);
+SPI_DMA_TX_CHANNEL(1, 6, 2);
+SPI_DMA_TX_CHANNEL(1, 7, 2);
+SPI_DMA_TX_CHANNEL(2, 1, 2);
+SPI_DMA_TX_CHANNEL(2, 2, 2);
+SPI_DMA_TX_CHANNEL(2, 3, 2);
+SPI_DMA_TX_CHANNEL(2, 4, 2);
+SPI_DMA_TX_CHANNEL(2, 5, 2);
+SPI_DMA_TX_CHANNEL(2, 6, 2);
+SPI_DMA_TX_CHANNEL(2, 7, 2);
+
+SPI_DMA_TX_CHANNEL(1, 1, 3);
+SPI_DMA_TX_CHANNEL(1, 2, 3);
+SPI_DMA_TX_CHANNEL(1, 3, 3);
+SPI_DMA_TX_CHANNEL(1, 4, 3);
+SPI_DMA_TX_CHANNEL(1, 5, 3);
+SPI_DMA_TX_CHANNEL(1, 6, 3);
+SPI_DMA_TX_CHANNEL(1, 7, 3);
+SPI_DMA_TX_CHANNEL(2, 1, 3);
+SPI_DMA_TX_CHANNEL(2, 2, 3);
+SPI_DMA_TX_CHANNEL(2, 3, 3);
+SPI_DMA_TX_CHANNEL(2, 4, 3);
+SPI_DMA_TX_CHANNEL(2, 5, 3);
+SPI_DMA_TX_CHANNEL(2, 6, 3);
+SPI_DMA_TX_CHANNEL(2, 7, 3);
+
+#if defined(SPI4)
+SPI_DMA_TX_CHANNEL(1, 1, 4);
+SPI_DMA_TX_CHANNEL(1, 2, 4);
+SPI_DMA_TX_CHANNEL(1, 3, 4);
+SPI_DMA_TX_CHANNEL(1, 4, 4);
+SPI_DMA_TX_CHANNEL(1, 5, 4);
+SPI_DMA_TX_CHANNEL(1, 6, 4);
+SPI_DMA_TX_CHANNEL(1, 7, 4);
+SPI_DMA_TX_CHANNEL(2, 1, 4);
+SPI_DMA_TX_CHANNEL(2, 2, 4);
+SPI_DMA_TX_CHANNEL(2, 3, 4);
+SPI_DMA_TX_CHANNEL(2, 4, 4);
+SPI_DMA_TX_CHANNEL(2, 5, 4);
+SPI_DMA_TX_CHANNEL(2, 6, 4);
+SPI_DMA_TX_CHANNEL(2, 7, 4);
+#endif
diff --git a/hw/bus/drivers/spi_stm32/pkg.yml
b/hw/bus/drivers/spi_stm32/stm32g4xx/pkg.yml
similarity index 52%
copy from hw/bus/drivers/spi_stm32/pkg.yml
copy to hw/bus/drivers/spi_stm32/stm32g4xx/pkg.yml
index b1cfb709c..be0196f24 100644
--- a/hw/bus/drivers/spi_stm32/pkg.yml
+++ b/hw/bus/drivers/spi_stm32/stm32g4xx/pkg.yml
@@ -17,46 +17,12 @@
# under the License.
#
-pkg.name: hw/bus/drivers/spi_stm32
-pkg.description: SPI bus driver that uses ST HAL with interrupts and DMA
+pkg.name: hw/bus/drivers/spi_stm32/stm32g4xx
+pkg.description: STM32G4 specific part of STM32 SPI driver
pkg.author: "Apache Mynewt <d...@mynewt.apache.org>"
pkg.homepage: "http://mynewt.apache.org/";
pkg.keywords:
pkg.deps:
- hw/bus
- - hw/bus/drivers/spi_common
-
-pkg.deps.MCU_STM32F0:
- - hw/bus/drivers/spi_stm32/stm32f0xx
-
-pkg.deps.MCU_STM32F1:
- - hw/bus/drivers/spi_stm32/stm32f1xx
-
-pkg.deps.MCU_STM32F3:
- - hw/bus/drivers/spi_stm32/stm32f3xx
-
-pkg.deps.MCU_STM32F4:
- - hw/bus/drivers/spi_stm32/stm32f4xx
-
-pkg.deps.MCU_STM32F7:
- - hw/bus/drivers/spi_stm32/stm32f7xx
-
-pkg.deps.MCU_STM32L0:
- - hw/bus/drivers/spi_stm32/stm32l0xx
-
-pkg.deps.MCU_STM32L1:
- - hw/bus/drivers/spi_stm32/stm32l1xx
-
-pkg.deps.MCU_STM32L4:
- - hw/bus/drivers/spi_stm32/stm32l4xx
-
-pkg.deps.MCU_STM32U5:
- - hw/bus/drivers/spi_stm32/stm32u5xx
-
-pkg.deps.MCU_STM32WB:
- - hw/bus/drivers/spi_stm32/stm32wbxx
-
-pkg.deps.MCU_STM32H7:
- - hw/bus/drivers/spi_stm32/stm32h7xx
-
+ - hw/bus/drivers/spi_stm32
diff --git a/hw/bus/drivers/spi_stm32/stm32g4xx/src/spidmacfg.c
b/hw/bus/drivers/spi_stm32/stm32g4xx/src/spidmacfg.c
new file mode 100644
index 000000000..b64416047
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g4xx/src/spidmacfg.c
@@ -0,0 +1,182 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <spidmacfg.h>
+#include <stm32g4xx_hal_dma.h>
+#include <stm32_common/stm32_dma.h>
+
+#define SPI_DMA_RX_CHANNEL_DEFINE(dma, ch, spi_num) \
+ const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ## spi_num
## _rx = { \
+ DMA ## dma ## _CH ## ch, \
+ DMA ## dma ## _Channel ## ch ## _IRQn, \
+ stm32_dma ## dma ## _ ## ch ## _irq_handler, \
+ .regs = DMA ## dma ## _Channel ## ch, \
+ .init = { \
+ .Request = DMA_REQUEST_SPI ## spi_num ## _RX, \
+ .Direction = DMA_PERIPH_TO_MEMORY, \
+ .PeriphInc = DMA_PINC_DISABLE, \
+ .MemInc = DMA_MINC_ENABLE, \
+ .PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
+ .MemDataAlignment = DMA_MDATAALIGN_BYTE, \
+ .Mode = DMA_NORMAL, \
+ .Priority = DMA_PRIORITY_LOW, \
+ } \
+ }
+
+#define SPI_DMA_TX_CHANNEL_DEFINE(dma, ch, spi_num) \
+ const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ## spi_num
## _tx = { \
+ DMA ## dma ## _CH ## ch, \
+ DMA ## dma ## _Channel ## ch ## _IRQn, \
+ stm32_dma ## dma ## _ ## ch ## _irq_handler, \
+ .regs = DMA ## dma ## _Channel ## ch, \
+ .init = { \
+ .Request = DMA_REQUEST_SPI ## spi_num ## _TX, \
+ .Direction = DMA_MEMORY_TO_PERIPH, \
+ .PeriphInc = DMA_PINC_DISABLE, \
+ .MemInc = DMA_MINC_ENABLE, \
+ .PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
+ .MemDataAlignment = DMA_MDATAALIGN_BYTE, \
+ .Mode = DMA_NORMAL, \
+ .Priority = DMA_PRIORITY_LOW, \
+ } \
+ }
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 1, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 2, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 3, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 4, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 5, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 6, 1);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 7, 1);
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 1, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 2, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 3, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 4, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 5, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 6, 2);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 7, 2);
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 1, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 2, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 3, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 4, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 5, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 6, 3);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 7, 3);
+
+#if defined(SPI4)
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 1, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 2, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 3, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 4, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 5, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 6, 4);
+SPI_DMA_RX_CHANNEL_DEFINE(2, 7, 4);
+#endif
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 1, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 2, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 3, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 4, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 5, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 6, 1);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 7, 1);
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 1, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 2, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 3, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 4, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 5, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 6, 2);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 7, 2);
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 1, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 2, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 3, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 4, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 5, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 6, 3);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 7, 3);
+
+#if defined(SPI4)
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 1, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 2, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 3, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 4, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 5, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 6, 4);
+SPI_DMA_TX_CHANNEL_DEFINE(2, 7, 4);
+#endif
diff --git a/hw/bus/drivers/spi_stm32/stm32g4xx/syscfg.yml
b/hw/bus/drivers/spi_stm32/stm32g4xx/syscfg.yml
new file mode 100644
index 000000000..f1eaafa49
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g4xx/syscfg.yml
@@ -0,0 +1,66 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ SPI1_DMA_PRIORITY:
+ description: 'DMA priority for SPI1 RX and TX'
+ value: DMA_PRIORITY_LOW
+ SPI2_DMA_PRIORITY:
+ description: 'DMA priority for SPI2 RX and TX'
+ value: DMA_PRIORITY_LOW
+
+ SPI1_RX_DMA:
+ description: >
+ DMA channel to use for SPI1. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel1_spi1_rx
+ SPI1_TX_DMA:
+ description: >
+ DMA channel to use for SPI1. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel2_spi1_tx
+ SPI2_RX_DMA:
+ description: >
+ DMA channel to use for SPI2. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel3_spi2_rx
+ SPI2_TX_DMA:
+ description: >
+ DMA channel to use for SPI2. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel4_spi2_tx
+ SPI3_RX_DMA:
+ description: >
+ DMA channel to use for SPI3. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel1_spi3_rx
+ SPI3_TX_DMA:
+ description: >
+ DMA channel to use for SPI3. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel2_spi3_tx
+ SPI4_RX_DMA:
+ description: >
+ DMA channel to use for SPI4. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel3_spi4_rx
+ SPI4_TX_DMA:
+ description: >
+ DMA channel to use for SPI4. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel4_spi4_tx
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/cmsis_nvic.h
b/hw/mcu/stm/stm32g4xx/include/mcu/cmsis_nvic.h
new file mode 100644
index 000000000..a9d900394
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/cmsis_nvic.h
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MCU_CMSIS_NVIC_H
+#define MCU_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+extern uint32_t __isr_vector_start[];
+extern uint32_t __isr_vector_end[];
+
+/* Extract number of vectors from .interrupt section size */
+#define NVIC_NUM_VECTORS (__isr_vector_end - __isr_vector_start)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include <stm32g4xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/cortex_m4.h
b/hw/mcu/stm/stm32g4xx/include/mcu/cortex_m4.h
new file mode 100644
index 000000000..f2fa05f29
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/cortex_m4.h
@@ -0,0 +1,39 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_CORTEX_M4_H__
+#define __MCU_CORTEX_M4_H__
+
+#include "stm32g4xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+hal_debug_break(void)
+{
+ __BKPT(1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_CORTEX_M4_H__ */
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/mcu.h
b/hw/mcu/stm/stm32g4xx/include/mcu/mcu.h
new file mode 100644
index 000000000..4225bdb40
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/mcu.h
@@ -0,0 +1,38 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#include <stm32g4xx.h>
+#include <stm32_common/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SVC_IRQ_NUMBER SVC_IRQn
+
+#define STM32_SYSTEM_MEMORY 0x0BF90000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_MCU_H_ */
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/mcu_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/mcu_vectors.h
new file mode 100644
index 000000000..8d0fc8e9a
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/mcu_vectors.h
@@ -0,0 +1,42 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#if defined(STM32G431xx)
+#include "vectors/stm32g431xx_vectors.h"
+#elif defined(STM32G441xx)
+#include "vectors/stm32g441xx_vectors.h"
+#elif defined(STM32G471xx)
+#include "vectors/stm32g471xx_vectors.h"
+#elif defined(STM32G473xx)
+#include "vectors/stm32g473xx_vectors.h"
+#elif defined(STM32G483xx)
+#include "vectors/stm32g483xx_vectors.h"
+#elif defined(STM32G474xx)
+#include "vectors/stm32g474xx_vectors.h"
+#elif defined(STM32G484xx)
+#include "vectors/stm32g484xx_vectors.h"
+#elif defined(STM32G491xx)
+#include "vectors/stm32g491xx_vectors.h"
+#elif defined(STM32G4A1xx)
+#include "vectors/stm32g4a1xx_vectors.h"
+#elif defined(STM32GBK1CB)
+#include "vectors/stm32gbk1cb_vectors.h"
+#else
+#error "Please select first the target STM32G4xx device used in your
application (in stm32g4xx.h file)"
+#endif
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/stm32_hal.h
b/hw/mcu/stm/stm32g4xx/include/mcu/stm32_hal.h
new file mode 100644
index 000000000..c35eb0e18
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/stm32_hal.h
@@ -0,0 +1,81 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef STM32_HAL_H
+#define STM32_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <mcu/cortex_m4.h>
+
+#include "stm32g4xx_hal.h"
+#include "stm32g4xx_hal_def.h"
+#include "stm32g4xx.h"
+#include "stm32g4xx_hal_dma.h"
+#include "stm32g4xx_hal_spi.h"
+#include "stm32g4xx_hal_gpio.h"
+#include "stm32g4xx_hal_gpio_ex.h"
+#include "stm32g4xx_hal_rcc.h"
+#include "stm32g4xx_hal_iwdg.h"
+#include "stm32g4xx_hal_i2c.h"
+#include "stm32g4xx_hal_uart.h"
+#include "mcu/stm32g4_bsp.h"
+#include "stm32g4xx_hal_tim.h"
+#include "stm32g4xx_ll_bus.h"
+#include "stm32g4xx_ll_tim.h"
+#include "stm32g4xx_hal_def.h"
+#include "stm32g4xx_hal_flash.h"
+#include "stm32g4xx_hal_flash_ex.h"
+#include "stm32g4xx_mynewt_hal.h"
+
+#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \
+ do { \
+ (x)->Init.Window = IWDG_WINDOW_DISABLE; \
+ } while (0)
+
+#define STM32_HAL_FLASH_REMAP()
+
+struct stm32_hal_spi_cfg {
+ int ss_pin; /* for slave mode */
+ int sck_pin;
+ int miso_pin;
+ int mosi_pin;
+ int irq_prio;
+};
+
+#define STM32_HAL_TIMER_MAX (3)
+
+#define STM32_HAL_TIMER_TIM1_IRQ TIM1_UP_TIM16_IRQn
+#define STM32_HAL_TIMER_TIM6_IRQ TIM6_DAC_IRQn
+#define STM32_HAL_TIMER_TIM8_IRQ TIM8_UP_IRQn
+
+#define STM32_HAL_FLASH_INIT() \
+ do { \
+ HAL_FLASH_Unlock(); \
+ } while (0)
+#define FLASH_PROGRAM_TYPE FLASH_TYPEPROGRAM_DOUBLEWORD
+#define STM32_HAL_FLASH_CLEAR_ERRORS()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_H */
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4_bsp.h
b/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4_bsp.h
new file mode 100644
index 000000000..c6ac716d3
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4_bsp.h
@@ -0,0 +1,57 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32G4_BSP_H_
+#define __MCU_STM32G4_BSP_H_
+
+#include <hal/hal_gpio.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * BSP specific UART settings.
+ */
+struct stm32_uart_cfg {
+ USART_TypeDef *suc_uart; /* UART dev registers */
+ volatile uint32_t *suc_rcc_reg; /* RCC register to modify */
+ uint32_t suc_rcc_dev; /* RCC device ID */
+ int8_t suc_pin_tx; /* pins for IO */
+ int8_t suc_pin_rx;
+ int8_t suc_pin_rts;
+ int8_t suc_pin_cts;
+ uint8_t suc_pin_af; /* AF selection for this */
+ IRQn_Type suc_irqn; /* NVIC IRQn */
+};
+
+/*
+ * Internal API for stm32u5xx mcu specific code.
+ */
+int hal_gpio_init_af(int pin, uint8_t af_type, enum hal_gpio_pull pull,
uint8_t od);
+
+struct hal_flash;
+extern struct hal_flash stm32g4_flash_dev;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32G4_BSP_H_ */
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4xx_mynewt_hal.h
b/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4xx_mynewt_hal.h
new file mode 100644
index 000000000..5afd63d47
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/stm32g4xx_mynewt_hal.h
@@ -0,0 +1,67 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32G4_MYNEWT_HAL_H
+#define __MCU_STM32G4_MYNEWT_HAL_H
+
+#include "stm32g4xx.h"
+#include "stm32g4xx_hal_dma.h"
+#include "stm32g4xx_hal_gpio.h"
+#include "stm32g4xx_hal_i2c.h"
+#include "stm32g4xx_hal_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while(0);
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while(0);
+
+
+int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg);
+int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg);
+
+struct stm32_hal_i2c_cfg {
+ I2C_TypeDef *hic_i2c;
+ volatile uint32_t *hic_rcc_reg; /* RCC register to modify */
+ uint32_t hic_rcc_dev; /* RCC device ID */
+ uint8_t hic_pin_sda;
+ uint8_t hic_pin_scl;
+ uint8_t hic_pin_af;
+ uint8_t hic_10bit;
+ uint32_t hic_timingr; /* TIMINGR register */
+ uint32_t hic_speed; /* Requested speed (used when
hic_timingr is 0) */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32G4_MYNEWT_HAL_H */
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g431xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g431xx_vectors.h
new file mode 100644
index 000000000..08566f8aa
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g431xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g441xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g441xx_vectors.h
new file mode 100644
index 000000000..a317521a4
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g441xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(AES_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g471xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g471xx_vectors.h
new file mode 100644
index 000000000..107a2673c
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g471xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(TIM5_IRQHandler)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR(I2C4_EV_IRQHandler)
+INT_VECTOR(I2C4_ER_IRQHandler)
+INT_VECTOR(SPI4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g473xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g473xx_vectors.h
new file mode 100644
index 000000000..487bae10b
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g473xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR(FMC_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(TIM5_IRQHandler)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_DAC_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR(ADC4_IRQHandler)
+INT_VECTOR(ADC5_IRQHandler)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_5_6_IRQHandler)
+INT_VECTOR(COMP7_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR(I2C4_EV_IRQHandler)
+INT_VECTOR(I2C4_ER_IRQHandler)
+INT_VECTOR(SPI4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR(FDCAN3_IT0_IRQHandler)
+INT_VECTOR(FDCAN3_IT1_IRQHandler)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g474xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g474xx_vectors.h
new file mode 100644
index 000000000..675721f91
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g474xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR(FMC_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(TIM5_IRQHandler)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_DAC_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR(ADC4_IRQHandler)
+INT_VECTOR(ADC5_IRQHandler)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_5_6_IRQHandler)
+INT_VECTOR(COMP7_IRQHandler)
+INT_VECTOR(HRTIM1_Master_IRQHandler)
+INT_VECTOR(HRTIM1_TIMA_IRQHandler)
+INT_VECTOR(HRTIM1_TIMB_IRQHandler)
+INT_VECTOR(HRTIM1_TIMC_IRQHandler)
+INT_VECTOR(HRTIM1_TIMD_IRQHandler)
+INT_VECTOR(HRTIM1_TIME_IRQHandler)
+INT_VECTOR(HRTIM1_FLT_IRQHandler)
+INT_VECTOR(HRTIM1_TIMF_IRQHandler)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR(I2C4_EV_IRQHandler)
+INT_VECTOR(I2C4_ER_IRQHandler)
+INT_VECTOR(SPI4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR(FDCAN3_IT0_IRQHandler)
+INT_VECTOR(FDCAN3_IT1_IRQHandler)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g483xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g483xx_vectors.h
new file mode 100644
index 000000000..0a30b13d7
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g483xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR(FMC_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(TIM5_IRQHandler)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_DAC_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR(ADC4_IRQHandler)
+INT_VECTOR(ADC5_IRQHandler)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_5_6_IRQHandler)
+INT_VECTOR(COMP7_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR(I2C4_EV_IRQHandler)
+INT_VECTOR(I2C4_ER_IRQHandler)
+INT_VECTOR(SPI4_IRQHandler)
+INT_VECTOR(AES_IRQHandler)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR(FDCAN3_IT0_IRQHandler)
+INT_VECTOR(FDCAN3_IT1_IRQHandler)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g484xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g484xx_vectors.h
new file mode 100644
index 000000000..769cc7aef
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g484xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR(FMC_IRQHandler)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR(TIM5_IRQHandler)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_DAC_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR(ADC4_IRQHandler)
+INT_VECTOR(ADC5_IRQHandler)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_5_6_IRQHandler)
+INT_VECTOR(COMP7_IRQHandler)
+INT_VECTOR(HRTIM1_Master_IRQHandler)
+INT_VECTOR(HRTIM1_TIMA_IRQHandler)
+INT_VECTOR(HRTIM1_TIMB_IRQHandler)
+INT_VECTOR(HRTIM1_TIMC_IRQHandler)
+INT_VECTOR(HRTIM1_TIMD_IRQHandler)
+INT_VECTOR(HRTIM1_TIME_IRQHandler)
+INT_VECTOR(HRTIM1_FLT_IRQHandler)
+INT_VECTOR(HRTIM1_TIMF_IRQHandler)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR(I2C4_EV_IRQHandler)
+INT_VECTOR(I2C4_ER_IRQHandler)
+INT_VECTOR(SPI4_IRQHandler)
+INT_VECTOR(AES_IRQHandler)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR(FDCAN3_IT0_IRQHandler)
+INT_VECTOR(FDCAN3_IT1_IRQHandler)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g491xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g491xx_vectors.h
new file mode 100644
index 000000000..0324b08a8
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g491xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g4a1xx_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g4a1xx_vectors.h
new file mode 100644
index 000000000..517391855
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32g4a1xx_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR(DMA1_Channel7_IRQHandler)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR(ADC3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR(UART4_IRQHandler)
+INT_VECTOR(UART5_IRQHandler)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR(TIM20_BRK_IRQHandler)
+INT_VECTOR(TIM20_UP_IRQHandler)
+INT_VECTOR(TIM20_TRG_COM_IRQHandler)
+INT_VECTOR(TIM20_CC_IRQHandler)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(AES_IRQHandler)
+INT_VECTOR(FDCAN2_IT0_IRQHandler)
+INT_VECTOR(FDCAN2_IT1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR(QUADSPI_IRQHandler)
+INT_VECTOR(DMA1_Channel8_IRQHandler)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR(DMA2_Channel7_IRQHandler)
+INT_VECTOR(DMA2_Channel8_IRQHandler)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32gbk1cb_vectors.h
b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32gbk1cb_vectors.h
new file mode 100644
index 000000000..16427cfbe
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/include/mcu/vectors/stm32gbk1cb_vectors.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+INT_VECTOR_STACK_TOP(__StackTop)
+INT_VECTOR_RESET_HANDLER(Reset_Handler)
+INT_VECTOR_NMI_HANDLER(NMI_Handler)
+INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler)
+INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler)
+INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler)
+INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_SVC_HANDLER(SVC_Handler)
+INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_PENDSV_HANDLER(PendSV_Handler)
+INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler)
+INT_VECTOR(WWDG_IRQHandler)
+INT_VECTOR(PVD_PVM_IRQHandler)
+INT_VECTOR(RTC_TAMP_LSECSS_IRQHandler)
+INT_VECTOR(RTC_WKUP_IRQHandler)
+INT_VECTOR(FLASH_IRQHandler)
+INT_VECTOR(RCC_IRQHandler)
+INT_VECTOR(EXTI0_IRQHandler)
+INT_VECTOR(EXTI1_IRQHandler)
+INT_VECTOR(EXTI2_IRQHandler)
+INT_VECTOR(EXTI3_IRQHandler)
+INT_VECTOR(EXTI4_IRQHandler)
+INT_VECTOR(DMA1_Channel1_IRQHandler)
+INT_VECTOR(DMA1_Channel2_IRQHandler)
+INT_VECTOR(DMA1_Channel3_IRQHandler)
+INT_VECTOR(DMA1_Channel4_IRQHandler)
+INT_VECTOR(DMA1_Channel5_IRQHandler)
+INT_VECTOR(DMA1_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(ADC1_2_IRQHandler)
+INT_VECTOR(USB_HP_IRQHandler)
+INT_VECTOR(USB_LP_IRQHandler)
+INT_VECTOR(FDCAN1_IT0_IRQHandler)
+INT_VECTOR(FDCAN1_IT1_IRQHandler)
+INT_VECTOR(EXTI9_5_IRQHandler)
+INT_VECTOR(TIM1_BRK_TIM15_IRQHandler)
+INT_VECTOR(TIM1_UP_TIM16_IRQHandler)
+INT_VECTOR(TIM1_TRG_COM_TIM17_IRQHandler)
+INT_VECTOR(TIM1_CC_IRQHandler)
+INT_VECTOR(TIM2_IRQHandler)
+INT_VECTOR(TIM3_IRQHandler)
+INT_VECTOR(TIM4_IRQHandler)
+INT_VECTOR(I2C1_EV_IRQHandler)
+INT_VECTOR(I2C1_ER_IRQHandler)
+INT_VECTOR(I2C2_EV_IRQHandler)
+INT_VECTOR(I2C2_ER_IRQHandler)
+INT_VECTOR(SPI1_IRQHandler)
+INT_VECTOR(SPI2_IRQHandler)
+INT_VECTOR(USART1_IRQHandler)
+INT_VECTOR(USART2_IRQHandler)
+INT_VECTOR(USART3_IRQHandler)
+INT_VECTOR(EXTI15_10_IRQHandler)
+INT_VECTOR(RTC_Alarm_IRQHandler)
+INT_VECTOR(USBWakeUp_IRQHandler)
+INT_VECTOR(TIM8_BRK_IRQHandler)
+INT_VECTOR(TIM8_UP_IRQHandler)
+INT_VECTOR(TIM8_TRG_COM_IRQHandler)
+INT_VECTOR(TIM8_CC_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(LPTIM1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(SPI3_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(TIM6_DAC_IRQHandler)
+INT_VECTOR(TIM7_IRQHandler)
+INT_VECTOR(DMA2_Channel1_IRQHandler)
+INT_VECTOR(DMA2_Channel2_IRQHandler)
+INT_VECTOR(DMA2_Channel3_IRQHandler)
+INT_VECTOR(DMA2_Channel4_IRQHandler)
+INT_VECTOR(DMA2_Channel5_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(UCPD1_IRQHandler)
+INT_VECTOR(COMP1_2_3_IRQHandler)
+INT_VECTOR(COMP4_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CRS_IRQHandler)
+INT_VECTOR(SAI1_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(FPU_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(RNG_IRQHandler)
+INT_VECTOR(LPUART1_IRQHandler)
+INT_VECTOR(I2C3_EV_IRQHandler)
+INT_VECTOR(I2C3_ER_IRQHandler)
+INT_VECTOR(DMAMUX_OVR_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(DMA2_Channel6_IRQHandler)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR_UNUSED(0)
+INT_VECTOR(CORDIC_IRQHandler)
+INT_VECTOR(FMAC_IRQHandler)
diff --git a/hw/mcu/stm/stm32g4xx/pkg.yml b/hw/mcu/stm/stm32g4xx/pkg.yml
new file mode 100644
index 000000000..edbc73bc0
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/pkg.yml
@@ -0,0 +1,65 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/stm/stm32g4xx
+pkg.description: MCU definition for STM32G4 ARM Cortex-M4 chips.
+pkg.author: "Apache Mynewt <d...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/";
+pkg.keywords:
+ - stm32
+ - stm32g4
+
+pkg.type: sdk
+
+pkg.ign_files:
+ - ".*template.*"
+
+pkg.include_dirs:
+ - "@stm-cmsis_device_g4/Include"
+ - "@stm-stm32g4xx_hal_driver/Inc"
+
+pkg.src_dirs:
+ - "@stm-stm32g4xx_hal_driver/Src"
+ - "src"
+
+pkg.ign_dirs:
+ - "Device"
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/boot/startup"
+
+pkg.deps.'(SPI_0_MASTER || SPI_1_MASTER || SPI_2_MASTER) &&
BUS_DRIVER_PRESENT':
+ - "@apache-mynewt-core/hw/bus/drivers/spi_stm32"
+
+repository.stm-cmsis_device_g4:
+ type: github
+ vers: v1.2.0-commit
+ branch: master
+ user: STMicroelectronics
+ repo: cmsis_device_g4
+
+repository.stm-stm32g4xx_hal_driver:
+ type: github
+ vers: v1.2.0-commit
+ branch: master
+ user: STMicroelectronics
+ repo: stm32g4xx_hal_driver
diff --git a/hw/mcu/stm/stm32g4xx/src/clock_stm32g4xx.c
b/hw/mcu/stm/stm32g4xx/src/clock_stm32g4xx.c
new file mode 100644
index 000000000..963631d90
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/clock_stm32g4xx.c
@@ -0,0 +1,244 @@
+/*
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without
modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
notice,
+ * this list of conditions and the following disclaimer in the
documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its
contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <stm32g4xx_hal_pwr_ex.h>
+#include <stm32g4xx_hal_rcc.h>
+#include <stm32g4xx_hal.h>
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__)
== RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__)
== RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__)
== RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) ||
((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) ==
RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) ==
RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+/*
+ * This allows an user to have a custom clock configuration by zeroing
+ * every possible clock source in the syscfg.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE) || \
+ MYNEWT_VAL(STM32_CLOCK_LSE) || MYNEWT_VAL(STM32_CLOCK_HSI) || \
+ MYNEWT_VAL(STM32_CLOCK_HSI48) || MYNEWT_VAL(STM32_CLOCK_LSI)
+
+#define TRNG_ENABLED (MYNEWT_VAL(TRNG) != 0)
+
+_Static_assert(MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_HSI),
+ "HSI and/or HSE must be enabled");
+
+void
+SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef osc_init = {};
+ RCC_ClkInitTypeDef clk_init = {};
+ HAL_StatusTypeDef status;
+#if TRNG_ENABLED
+ RCC_PeriphCLKInitTypeDef pclk_init;
+#endif
+
+ /*
+ * The voltage scaling allows optimizing the power consumption when the
+ * device is clocked below the maximum system frequency, to update the
+ * voltage scaling value regarding system frequency refer to product
+ * datasheet.
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
HAL_PWREx_ControlVoltageScaling(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG));
+
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+
+ /*
+ * LSI is used to clock the independent watchdog and optionally the RTC.
+ * It can be disabled per user request, but will be automatically enabled
+ * again when the IWDG is started.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
+ if (MYNEWT_VAL(STM32_CLOCK_LSI)) {
+ osc_init.LSIState = RCC_LSI_ON;
+ } else {
+ osc_init.LSIState = RCC_LSI_OFF;
+ }
+
+ /*
+ * LSE is only used to clock the RTC.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
+ if (MYNEWT_VAL(STM32_CLOCK_LSE)) {
+ if (MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS)) {
+ osc_init.LSEState = RCC_LSE_BYPASS;
+ } else {
+ osc_init.LSEState = RCC_LSE_ON;
+ }
+ } else {
+ osc_init.LSEState = RCC_LSE_OFF;
+ }
+
+ /*
+ * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source)
+ */
+ if (MYNEWT_VAL(STM32_CLOCK_HSE)) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+
+ if (MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS)) {
+ osc_init.HSEState = RCC_HSE_BYPASS;
+ } else {
+ osc_init.HSEState = RCC_HSE_ON;
+ }
+ }
+
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSI) ||
MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION) <= 127,
+ "Invalid HSI calibration value");
+ /*
+ * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is
+ * already turned on by default but a new calibration setting might be
+ * used. If the user chooses to turn it off, it must be turned off after
+ * SYSCLK was updated to use HSE/PLL.
+ */
+ if (MYNEWT_VAL(STM32_CLOCK_HSI)) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_ON;
+ /* HSI calibration is not optional when HSI is enabled */
+ osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION);
+ }
+
+ /*
+ * HSI48 can be used to drive USB/RNG
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+ if (MYNEWT_VAL(STM32_CLOCK_HSI48)) {
+ osc_init.HSI48State = RCC_HSI48_ON;
+ } else {
+ osc_init.HSI48State = RCC_HSI48_OFF;
+ }
+
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)),
+ "PLLM value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)),
+ "PLLN value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)),
+ "PLLP value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)),
+ "PLLQ value is invalid");
+ _Static_assert(!MYNEWT_VAL(STM32_CLOCK_PLL) ||
IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)),
+ "PLLR value is invalid");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_PLL) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, PLL_R),
+ "PLL selected as system clock but not enabled");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSE) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSE),
+ "HSE selected as system clock but not enabled");
+ _Static_assert(MYNEWT_VAL(STM32_CLOCK_HSI) ||
!MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSI),
+ "HSI selected as system clock but not enabled");
+
+ if (MYNEWT_VAL(STM32_CLOCK_PLL)) {
+ /*
+ * Default to MSI, HSE or HSI48 as PLL source when multiple high-speed
+ * sources are enabled.
+ */
+ osc_init.PLL.PLLState = RCC_PLL_ON;
+ if (MYNEWT_VAL(STM32_CLOCK_HSE)) {
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ } else {
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ }
+
+ osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM);
+ osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN);
+ osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP);
+ osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ);
+ osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR);
+ }
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ if (MYNEWT_VAL(STM32_CLOCK_PLL) &&
+ (MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, PLL_R) ||
MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, auto))) {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ } else if (MYNEWT_VAL(STM32_CLOCK_HSE) &&
+ (MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, HSE) ||
+ MYNEWT_VAL_CHOICE(STM32_CLOCK_SYSCLK, auto))) {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
+ } else {
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ }
+
+ _Static_assert(IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER)), "AHB
clock divider is invalid");
+ _Static_assert(IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER)), "APB1
clock divider is invalid");
+ _Static_assert(IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER)), "APB2
clock divider is invalid");
+
+ clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER);
+ clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER);
+ clk_init.APB2CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER);
+
+ _Static_assert(IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY)), "Flash
latency value is invalid");
+
+ status = HAL_RCC_ClockConfig(&clk_init, MYNEWT_VAL(STM32_FLASH_LATENCY));
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ if ((MYNEWT_VAL(STM32_CLOCK_HSI) == 0) || (MYNEWT_VAL(STM32_CLOCK_HSE) ==
0)) {
+ /*
+ * Turn off HSE/HSI oscillator; this must be done at the end because
+ * SYSCLK source has to be updated first.
+ */
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+ if (MYNEWT_VAL(STM32_CLOCK_HSE) == 0) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+ osc_init.HSEState = RCC_HSE_OFF;
+ }
+ if (MYNEWT_VAL(STM32_CLOCK_HSI) == 0) {
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_OFF;
+ }
+ }
+
+ osc_init.PLL.PLLState = RCC_PLL_NONE;
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+#if TRNG_ENABLED
+ pclk_init.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+ /* Other clock sources are possible, but since right now we always
+ * configure the PLL, this should be ok
+ */
+ pclk_init.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
+ status = HAL_RCCEx_PeriphCLKConfig(&pclk_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+#endif
+}
+#endif
diff --git a/hw/mcu/stm/stm32g4xx/src/hal_flash.c
b/hw/mcu/stm/stm32g4xx/src/hal_flash.c
new file mode 100644
index 000000000..69b8b7ee6
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/hal_flash.c
@@ -0,0 +1,56 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <syscfg/syscfg.h>
+#include <mcu/stm32_hal.h>
+#include "hal/hal_flash_int.h"
+
+#define STM32_FLASH_SIZE (MYNEWT_VAL(STM32_FLASH_SIZE_KB) * 1024)
+
+int
+stm32_mcu_flash_erase_sector(const struct hal_flash *dev, uint32_t
sector_address)
+{
+ FLASH_EraseInitTypeDef eraseinit;
+ uint32_t PageError;
+ HAL_StatusTypeDef rc;
+
+ (void)PageError;
+
+ if (!(sector_address & (FLASH_PAGE_SIZE - 1))) {
+ eraseinit.TypeErase = FLASH_TYPEERASE_PAGES;
+#ifdef FLASH_BANK_2
+ if ((sector_address - dev->hf_base_addr) < (STM32_FLASH_SIZE / 2)) {
+ eraseinit.Banks = FLASH_BANK_1;
+ }
+ else {
+ eraseinit.Banks = FLASH_BANK_2;
+ }
+#else
+ eraseinit.Banks = FLASH_BANK_1;
+#endif
+ eraseinit.Page = (sector_address - dev->hf_base_addr) /
FLASH_PAGE_SIZE;
+ eraseinit.NbPages = 1;
+ rc = HAL_FLASHEx_Erase(&eraseinit, &PageError);
+ if (rc == HAL_OK) {
+ return 0;
+ }
+ }
+
+ return -1;
+}
diff --git a/hw/mcu/stm/stm32g4xx/src/hal_reset_cause.c
b/hw/mcu/stm/stm32g4xx/src/hal_reset_cause.c
new file mode 100644
index 000000000..874341117
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/hal_reset_cause.c
@@ -0,0 +1,48 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <hal/hal_system.h>
+
+#include "stm32g4xx_hal_def.h"
+
+enum hal_reset_reason
+hal_reset_cause(void)
+{
+ static enum hal_reset_reason reason;
+ uint32_t reg;
+
+ if (reason) {
+ return reason;
+ }
+
+ reg = RCC->CSR;
+
+ if (reg & (RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF)) {
+ reason = HAL_RESET_WATCHDOG;
+ } else if (reg & RCC_CSR_SFTRSTF) {
+ reason = HAL_RESET_SOFT;
+ } else if (reg & RCC_CSR_PINRSTF) {
+ reason = HAL_RESET_PIN;
+ } else if (reg & (RCC_CSR_BORRSTF | RCC_CSR_LPWRRSTF)) {
+ reason = HAL_RESET_BROWNOUT;
+ } else {
+ reason = HAL_RESET_POR;
+ }
+ RCC->CSR |= RCC_CSR_RMVF;
+ return reason;
+}
diff --git a/hw/mcu/stm/stm32g4xx/src/hal_system_init.c
b/hw/mcu/stm/stm32g4xx/src/hal_system_init.c
new file mode 100644
index 000000000..414a4daf0
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/hal_system_init.c
@@ -0,0 +1,43 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/mynewt.h"
+#include "mcu/stm32_hal.h"
+#include <hal/hal_system.h>
+
+extern char __vector_tbl_reloc__[];
+
+void
+hal_system_init(void)
+{
+ SCB->VTOR = (uint32_t)&__vector_tbl_reloc__;
+
+ if (PREFETCH_ENABLE) {
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+ }
+
+ if (MYNEWT_VAL(STM32_ENABLE_ICACHE)) {
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ }
+
+ if (MYNEWT_VAL(STM32_ENABLE_DCACHE)) {
+ __HAL_FLASH_DATA_CACHE_ENABLE();
+ }
+}
+
diff --git a/hw/mcu/stm/stm32g4xx/src/hal_timer_freq.c
b/hw/mcu/stm/stm32g4xx/src/hal_timer_freq.c
new file mode 100644
index 000000000..0cdb3b714
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/hal_timer_freq.c
@@ -0,0 +1,96 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <inttypes.h>
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <hal/hal_timer.h>
+#include "mcu/stm32_hal.h"
+#include "stm32_common/stm32_hal.h"
+
+
+/*
+ * Generic implementation for determining the frequency
+ * of a timer.
+ */
+
+uint32_t
+stm32_hal_timer_get_freq(void *regs)
+{
+ RCC_ClkInitTypeDef clocks;
+ uint32_t fl;
+ uint32_t freq;
+
+ HAL_RCC_GetClockConfig(&clocks, &fl);
+
+ /*
+ * Assuming RCC_DCKCFGR->TIMPRE is 0.
+ * There's just APB2 timers here.
+ */
+ switch ((uintptr_t)regs) {
+#ifdef TIM1
+ case (uintptr_t)TIM1:
+#endif
+#ifdef TIM8
+ case (uintptr_t)TIM8:
+#endif
+#ifdef TIM9
+ case (uintptr_t)TIM9:
+#endif
+#ifdef TIM10
+ case (uintptr_t)TIM10:
+#endif
+#ifdef TIM11
+ case (uintptr_t)TIM11:
+#endif
+#ifdef TIM15
+ case (uintptr_t)TIM15:
+#endif
+#ifdef TIM16
+ case (uintptr_t)TIM16:
+#endif
+#ifdef TIM17
+ case (uintptr_t)TIM17:
+#endif
+ freq = HAL_RCC_GetPCLK2Freq();
+ if (clocks.APB2CLKDivider) {
+ freq *= 2;
+ }
+ break;
+#ifdef TIM2
+ case (uintptr_t)TIM2:
+#endif
+#ifdef TIM3
+ case (uintptr_t)TIM3:
+#endif
+#ifdef TIM4
+ case (uintptr_t)TIM4:
+#endif
+ freq = HAL_RCC_GetPCLK1Freq();
+ if (clocks.APB1CLKDivider) {
+ freq *= 2;
+ }
+ break;
+ default:
+ return 0;
+ }
+ return freq;
+}
diff --git a/hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c
b/hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c
new file mode 100644
index 000000000..83ba03567
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c
@@ -0,0 +1,297 @@
+/**
+
******************************************************************************
+ * @file system_stm32g4xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called
from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset
and
+ * before branch to main program. This call is made
inside
+ * the "startup_stm32g4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be
used
+ * by the user application to setup the
SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and
must
+ * be called whenever the core clock is
changed
+ * during program execution.
+ *
+ * After each device reset the HSI (16 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+
*=============================================================================
+
*-----------------------------------------------------------------------------
+ * System Clock source | HSI
+
*-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 16000000
+
*-----------------------------------------------------------------------------
+ * HCLK(Hz) | 16000000
+
*-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+
*-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+
*-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+
*-----------------------------------------------------------------------------
+ * PLL_M | 1
+
*-----------------------------------------------------------------------------
+ * PLL_N | 16
+
*-----------------------------------------------------------------------------
+ * PLL_P | 7
+
*-----------------------------------------------------------------------------
+ * PLL_Q | 2
+
*-----------------------------------------------------------------------------
+ * PLL_R | 2
+
*-----------------------------------------------------------------------------
+ * Require 48MHz for RNG | Disabled
+
*-----------------------------------------------------------------------------
+
*=============================================================================
+
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32g4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32G4xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32g4xx.h"
+#include <mcu/cmsis_nvic.h>
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz
*/
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration
************************/
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address
field.
+ This value must be a
multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset
field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address
field.
+ This value must be a
multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset
field.
+ This value must be a
multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system
clock frequency
+ Note: If you use this function to configure the system clock; then
there
+ is no need to call the 2 first functions listed above, since
SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = HSI_VALUE;
+
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U,
3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32G4xx_System_Private_Functions
+ * @{
+ */
+
+/*
+ * XXX BSP specific
+ */
+void SystemClock_Config(void);
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings
------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11
Full Access */
+ #endif
+
+ /* Configure the Vector Table location add offset address
------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table
Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+ /* Configure System Clock */
+ SystemClock_Config();
+
+ /* Update SystemCoreClock global variable */
+ SystemCoreClockUpdate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or
configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be
called
+ * to update SystemCoreClock variable value. Otherwise, any
configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the
HSE_VALUE(***)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file
(default value
+ * 16 MHz) but the real value may vary depending on the
variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file
(default value
+ * 24 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using
fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp, pllvco, pllr, pllsource, pllm;
+
+ /* Get SYSCLK source
-------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case 0x04: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case 0x08: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x0C: /* PLL used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
+ if (pllsource == 0x02UL) /* HSI used as PLL clock source */
+ {
+ pllvco = (HSI_VALUE / pllm);
+ }
+ else /* HSE used as PLL clock source */
+ {
+ pllvco = (HSE_VALUE / pllm);
+ }
+ pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
+ SystemCoreClock = pllvco/pllr;
+ break;
+
+ default:
+ break;
+ }
+ /* Compute HCLK clock frequency
--------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/hw/mcu/stm/stm32g4xx/stm32g4xx.ld
b/hw/mcu/stm/stm32g4xx/stm32g4xx.ld
new file mode 100644
index 000000000..e0b6bf2cf
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/stm32g4xx.ld
@@ -0,0 +1,209 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __coredata_start__
+ * __coredata_end__
+ * __corebss_start__
+ * __corebss_end__
+ * __ecoredata
+ * __ecorebss
+ */
+ENTRY(Reset_Handler)
+
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+SECTIONS
+{
+ /* Reserve space at the start of the image for the header. */
+ .imghdr (NOLOAD):
+ {
+ . = . + _imghdr_size;
+ } > FLASH
+
+ .text :
+ {
+ . = ALIGN(8);
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ PROVIDE(mynewt_main = main);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(8);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ } > RAM
+
+ .coredata :
+ {
+ . = ALIGN(8);
+ __coredata_start__ = .;
+ *(.data.core)
+ __coredata_end__ = .;
+ } > RAM AT > FLASH
+
+ __ecoredata = __etext + SIZEOF(.coredata);
+
+ _sidata = LOADADDR(.data);
+
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = .;
+ __data_start__ = _sdata;
+ *(vtable)
+ *(.data*)
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ _edata = .;
+ __data_end__ = _edata;
+
+ } > RAM AT > FLASH
+
+ .corebss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __corebss_start__ = .;
+ *(.bss.core)
+ . = ALIGN(4);
+ __corebss_end__ = .;
+ *(.corebss*)
+ *(.bss.core.nz)
+ . = ALIGN(4);
+ __ecorebss = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ } > RAM
+
+ . = ALIGN(8);
+ __HeapBase = .;
+ __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);
+
+ _ram_start = ORIGIN(RAM);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM; stack limit is bottom of stack */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+}
+
diff --git a/hw/mcu/stm/stm32g4xx/syscfg.yml b/hw/mcu/stm/stm32g4xx/syscfg.yml
new file mode 100644
index 000000000..5655870c9
--- /dev/null
+++ b/hw/mcu/stm/stm32g4xx/syscfg.yml
@@ -0,0 +1,149 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 8
+
+ MCU_STM32G4:
+ description: MCUs are of STM32G4xx family
+ value: 1
+
+ STM32_CLOCK_VOLTAGESCALING_CONFIG:
+ description: >
+ Adjust voltage scaling.
+ PWR_REGULATOR_VOLTAGE_SCALE1_BOOST for system clock > 150MHz
+ PWR_REGULATOR_VOLTAGE_SCALE1 for system clock up to 150MHz
+ PWR_REGULATOR_VOLTAGE_SCALE2 for system clock <= 26MHz
+ value: PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
+
+ STM32_CLOCK_LSI:
+ description: Enable low-speed internal clock source
+ value: 0
+
+ STM32_CLOCK_LSE:
+ description: Enable low-speed external clock source (aka RTC xtal)
+ value: 0
+
+ STM32_CLOCK_LSE_BYPASS:
+ description: 0 for 32768 xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSE:
+ description: Enable high-speed external clock source
+ value: 0
+
+ STM32_CLOCK_HSE_BYPASS:
+ description: 0 for xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSI:
+ description: Enable high-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_HSI_CALIBRATION:
+ description: HSI calibration value
+ value: 'RCC_HSICALIBRATION_DEFAULT'
+
+ STM32_CLOCK_HSI48:
+ description: Enable high-speed 48MHz internal clock source
+ value: 0
+
+ STM32_CLOCK_SYSCLK:
+ description: Select SYSCLK source
+ choices:
+ - HSI
+ - HSE
+ - PLL_R
+ - auto
+ value: auto
+
+ STM32_CLOCK_PLL:
+ description: Enable PLL
+ value: 0
+
+ STM32_CLOCK_PLL_PLLM:
+ description: PLL config M parameter
+ value: 4
+
+ STM32_CLOCK_PLL_PLLN:
+ description: PLL config N parameter
+ value: 85
+
+ STM32_CLOCK_PLL_PLLP:
+ description: PLL config P parameter
+ value: 2
+
+ STM32_CLOCK_PLL_PLLQ:
+ description: PLL config Q parameter
+ value: 2
+
+ STM32_CLOCK_PLL_PLLR:
+ description: PLL config R parameter
+ value: 2
+
+ STM32_CLOCK_AHB_DIVIDER:
+ description: AHB CLK1 prescaler
+ value: RCC_SYSCLK_DIV1
+
+ STM32_CLOCK_APB1_DIVIDER:
+ description: APB1 prescaler
+ value: RCC_HCLK_DIV1
+
+ STM32_CLOCK_APB2_DIVIDER:
+ description: APB2 prescaler
+ value: RCC_HCLK_DIV1
+
+ STM32_FLASH_LATENCY:
+ description: Number of wait-states
+ value: FLASH_LATENCY_4
+
+ STM32_ENABLE_ICACHE:
+ description: Enable instruction caching
+ value: 1
+
+ STM32_ENABLE_DCACHE:
+ description: Enable instruction caching
+ value: 1
+
+ STM32_FLASH_PREFETCH_ENABLE:
+ description: Enable pre-fetch of instructions (when latency > 0)
+ value: 1
+
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI with FIFO
+ value: 1
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has no clock speed register (has TIMINGR)
+ value: 0
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses ISR register (not SR) for status.
+ value: 0
+
+ MCU_FLASH_ERASED_VAL:
+ description: Value read from erased flash.
+ value: 0xff
+
+syscfg.vals:
+ MCU_RAM_START: 0x20000000
+ MCU_RAM_SIZE: 0x1C000
