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jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new 3fbf85d2a hw/bus/spi_stm32: Add DMA configuration for STM32G0
3fbf85d2a is described below
commit 3fbf85d2aa7d819cfe2daaa8f82d4a3373a329f4
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Tue Mar 5 14:07:39 2024 +0100
hw/bus/spi_stm32: Add DMA configuration for STM32G0
Bus driver for STM32 requires DMA configuration that went
missing when STM32G0 support was added
Signed-off-by: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
---
hw/bus/drivers/spi_stm32/pkg.yml | 3 +
.../spi_stm32/stm32g0xx/include/spidmacfg.h | 137 +++++++++++++++++++++
hw/bus/drivers/spi_stm32/{ => stm32g0xx}/pkg.yml | 43 +------
hw/bus/drivers/spi_stm32/stm32g0xx/src/spidmacfg.c | 113 +++++++++++++++++
hw/bus/drivers/spi_stm32/stm32g0xx/syscfg.yml | 66 ++++++++++
5 files changed, 322 insertions(+), 40 deletions(-)
diff --git a/hw/bus/drivers/spi_stm32/pkg.yml b/hw/bus/drivers/spi_stm32/pkg.yml
index 890359db8..38f9fdbb7 100644
--- a/hw/bus/drivers/spi_stm32/pkg.yml
+++ b/hw/bus/drivers/spi_stm32/pkg.yml
@@ -42,6 +42,9 @@ pkg.deps.MCU_STM32F4:
pkg.deps.MCU_STM32F7:
- hw/bus/drivers/spi_stm32/stm32f7xx
+pkg.deps.MCU_STM32G0:
+ - hw/bus/drivers/spi_stm32/stm32g0xx
+
pkg.deps.MCU_STM32G4:
- hw/bus/drivers/spi_stm32/stm32g4xx
diff --git a/hw/bus/drivers/spi_stm32/stm32g0xx/include/spidmacfg.h
b/hw/bus/drivers/spi_stm32/stm32g0xx/include/spidmacfg.h
new file mode 100644
index 000000000..c5a3747b0
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g0xx/include/spidmacfg.h
@@ -0,0 +1,137 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stm32g0xx_hal_dma.h>
+
+struct stm32_dma_cfg {
+ uint8_t dma_ch;
+ uint8_t irqn;
+ void (*irq_handler)(void);
+ DMA_Channel_TypeDef *regs;
+ DMA_InitTypeDef init;
+};
+
+#define SPI_DMA_RX_CHANNEL(dma, ch, spi_num) \
+ extern const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ##
spi_num ## _rx;
+
+#define SPI_DMA_TX_CHANNEL(dma, ch, spi_num) \
+ extern const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ##
spi_num ## _tx;
+
+SPI_DMA_RX_CHANNEL(1, 1, 1);
+SPI_DMA_RX_CHANNEL(1, 2, 1);
+SPI_DMA_RX_CHANNEL(1, 3, 1);
+SPI_DMA_RX_CHANNEL(1, 4, 1);
+SPI_DMA_RX_CHANNEL(1, 5, 1);
+SPI_DMA_RX_CHANNEL(1, 6, 1);
+SPI_DMA_RX_CHANNEL(1, 7, 1);
+#ifdef DMA2
+SPI_DMA_RX_CHANNEL(2, 1, 1);
+SPI_DMA_RX_CHANNEL(2, 2, 1);
+SPI_DMA_RX_CHANNEL(2, 3, 1);
+SPI_DMA_RX_CHANNEL(2, 4, 1);
+SPI_DMA_RX_CHANNEL(2, 5, 1);
+SPI_DMA_RX_CHANNEL(2, 6, 1);
+SPI_DMA_RX_CHANNEL(2, 7, 1);
+#endif
+
+SPI_DMA_RX_CHANNEL(1, 1, 2);
+SPI_DMA_RX_CHANNEL(1, 2, 2);
+SPI_DMA_RX_CHANNEL(1, 3, 2);
+SPI_DMA_RX_CHANNEL(1, 4, 2);
+SPI_DMA_RX_CHANNEL(1, 5, 2);
+SPI_DMA_RX_CHANNEL(1, 6, 2);
+SPI_DMA_RX_CHANNEL(1, 7, 2);
+#ifdef DMA2
+SPI_DMA_RX_CHANNEL(2, 1, 2);
+SPI_DMA_RX_CHANNEL(2, 2, 2);
+SPI_DMA_RX_CHANNEL(2, 3, 2);
+SPI_DMA_RX_CHANNEL(2, 4, 2);
+SPI_DMA_RX_CHANNEL(2, 5, 2);
+SPI_DMA_RX_CHANNEL(2, 6, 2);
+SPI_DMA_RX_CHANNEL(2, 7, 2);
+#endif
+
+SPI_DMA_RX_CHANNEL(1, 1, 3);
+SPI_DMA_RX_CHANNEL(1, 2, 3);
+SPI_DMA_RX_CHANNEL(1, 3, 3);
+SPI_DMA_RX_CHANNEL(1, 4, 3);
+SPI_DMA_RX_CHANNEL(1, 5, 3);
+SPI_DMA_RX_CHANNEL(1, 6, 3);
+SPI_DMA_RX_CHANNEL(1, 7, 3);
+#ifdef DMA2
+SPI_DMA_RX_CHANNEL(2, 1, 3);
+SPI_DMA_RX_CHANNEL(2, 2, 3);
+SPI_DMA_RX_CHANNEL(2, 3, 3);
+SPI_DMA_RX_CHANNEL(2, 4, 3);
+SPI_DMA_RX_CHANNEL(2, 5, 3);
+SPI_DMA_RX_CHANNEL(2, 6, 3);
+SPI_DMA_RX_CHANNEL(2, 7, 3);
+#endif
+
+SPI_DMA_TX_CHANNEL(1, 1, 1);
+SPI_DMA_TX_CHANNEL(1, 2, 1);
+SPI_DMA_TX_CHANNEL(1, 3, 1);
+SPI_DMA_TX_CHANNEL(1, 4, 1);
+SPI_DMA_TX_CHANNEL(1, 5, 1);
+SPI_DMA_TX_CHANNEL(1, 6, 1);
+SPI_DMA_TX_CHANNEL(1, 7, 1);
+#ifdef DMA2
+SPI_DMA_TX_CHANNEL(2, 1, 1);
+SPI_DMA_TX_CHANNEL(2, 2, 1);
+SPI_DMA_TX_CHANNEL(2, 3, 1);
+SPI_DMA_TX_CHANNEL(2, 4, 1);
+SPI_DMA_TX_CHANNEL(2, 5, 1);
+SPI_DMA_TX_CHANNEL(2, 6, 1);
+SPI_DMA_TX_CHANNEL(2, 7, 1);
+#endif
+
+SPI_DMA_TX_CHANNEL(1, 1, 2);
+SPI_DMA_TX_CHANNEL(1, 2, 2);
+SPI_DMA_TX_CHANNEL(1, 3, 2);
+SPI_DMA_TX_CHANNEL(1, 4, 2);
+SPI_DMA_TX_CHANNEL(1, 5, 2);
+SPI_DMA_TX_CHANNEL(1, 6, 2);
+SPI_DMA_TX_CHANNEL(1, 7, 2);
+#ifdef DMA2
+SPI_DMA_TX_CHANNEL(2, 1, 2);
+SPI_DMA_TX_CHANNEL(2, 2, 2);
+SPI_DMA_TX_CHANNEL(2, 3, 2);
+SPI_DMA_TX_CHANNEL(2, 4, 2);
+SPI_DMA_TX_CHANNEL(2, 5, 2);
+SPI_DMA_TX_CHANNEL(2, 6, 2);
+SPI_DMA_TX_CHANNEL(2, 7, 2);
+#endif
+
+SPI_DMA_TX_CHANNEL(1, 1, 3);
+SPI_DMA_TX_CHANNEL(1, 2, 3);
+SPI_DMA_TX_CHANNEL(1, 3, 3);
+SPI_DMA_TX_CHANNEL(1, 4, 3);
+SPI_DMA_TX_CHANNEL(1, 5, 3);
+SPI_DMA_TX_CHANNEL(1, 6, 3);
+SPI_DMA_TX_CHANNEL(1, 7, 3);
+#ifdef DMA2
+SPI_DMA_TX_CHANNEL(2, 1, 3);
+SPI_DMA_TX_CHANNEL(2, 2, 3);
+SPI_DMA_TX_CHANNEL(2, 3, 3);
+SPI_DMA_TX_CHANNEL(2, 4, 3);
+SPI_DMA_TX_CHANNEL(2, 5, 3);
+SPI_DMA_TX_CHANNEL(2, 6, 3);
+SPI_DMA_TX_CHANNEL(2, 7, 3);
+#endif
diff --git a/hw/bus/drivers/spi_stm32/pkg.yml
b/hw/bus/drivers/spi_stm32/stm32g0xx/pkg.yml
similarity index 50%
copy from hw/bus/drivers/spi_stm32/pkg.yml
copy to hw/bus/drivers/spi_stm32/stm32g0xx/pkg.yml
index 890359db8..37d9ebede 100644
--- a/hw/bus/drivers/spi_stm32/pkg.yml
+++ b/hw/bus/drivers/spi_stm32/stm32g0xx/pkg.yml
@@ -17,49 +17,12 @@
# under the License.
#
-pkg.name: hw/bus/drivers/spi_stm32
-pkg.description: SPI bus driver that uses ST HAL with interrupts and DMA
+pkg.name: hw/bus/drivers/spi_stm32/stm32g0xx
+pkg.description: STM32G0 specific part of STM32 SPI driver
pkg.author: "Apache Mynewt <d...@mynewt.apache.org>"
pkg.homepage: "http://mynewt.apache.org/";
pkg.keywords:
pkg.deps:
- hw/bus
- - hw/bus/drivers/spi_common
-
-pkg.deps.MCU_STM32F0:
- - hw/bus/drivers/spi_stm32/stm32f0xx
-
-pkg.deps.MCU_STM32F1:
- - hw/bus/drivers/spi_stm32/stm32f1xx
-
-pkg.deps.MCU_STM32F3:
- - hw/bus/drivers/spi_stm32/stm32f3xx
-
-pkg.deps.MCU_STM32F4:
- - hw/bus/drivers/spi_stm32/stm32f4xx
-
-pkg.deps.MCU_STM32F7:
- - hw/bus/drivers/spi_stm32/stm32f7xx
-
-pkg.deps.MCU_STM32G4:
- - hw/bus/drivers/spi_stm32/stm32g4xx
-
-pkg.deps.MCU_STM32L0:
- - hw/bus/drivers/spi_stm32/stm32l0xx
-
-pkg.deps.MCU_STM32L1:
- - hw/bus/drivers/spi_stm32/stm32l1xx
-
-pkg.deps.MCU_STM32L4:
- - hw/bus/drivers/spi_stm32/stm32l4xx
-
-pkg.deps.MCU_STM32U5:
- - hw/bus/drivers/spi_stm32/stm32u5xx
-
-pkg.deps.MCU_STM32WB:
- - hw/bus/drivers/spi_stm32/stm32wbxx
-
-pkg.deps.MCU_STM32H7:
- - hw/bus/drivers/spi_stm32/stm32h7xx
-
+ - hw/bus/drivers/spi_stm32
diff --git a/hw/bus/drivers/spi_stm32/stm32g0xx/src/spidmacfg.c
b/hw/bus/drivers/spi_stm32/stm32g0xx/src/spidmacfg.c
new file mode 100644
index 000000000..8eaca5ee2
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g0xx/src/spidmacfg.c
@@ -0,0 +1,113 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <spidmacfg.h>
+#include <stm32g0xx_hal_dma.h>
+#include <stm32_common/stm32_dma.h>
+
+#define DMA1_Channel2_IRQn 10
+#define DMA1_Channel3_IRQn 10
+#define DMA1_Channel4_IRQn 11
+#define DMA1_Channel5_IRQn 11
+#define DMA1_Channel6_IRQn 11
+#define DMA1_Channel7_IRQn 11
+
+#define SPI_DMA_RX_CHANNEL_DEFINE(dma, ch, spi_num, irq_handler) \
+ const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ## spi_num
## _rx = { \
+ DMA ## dma ## _CH ## ch, \
+ DMA ## dma ## _Channel ## ch ## _IRQn, \
+ irq_handler, \
+ .regs = DMA ## dma ## _Channel ## ch, \
+ .init = { \
+ .Request = DMA_REQUEST_SPI ## spi_num ## _RX, \
+ .Direction = DMA_PERIPH_TO_MEMORY, \
+ .PeriphInc = DMA_PINC_DISABLE, \
+ .MemInc = DMA_MINC_ENABLE, \
+ .PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
+ .MemDataAlignment = DMA_MDATAALIGN_BYTE, \
+ .Mode = DMA_NORMAL, \
+ .Priority = DMA_PRIORITY_LOW, \
+ } \
+ }
+
+#define SPI_DMA_TX_CHANNEL_DEFINE(dma, ch, spi_num, irq_handler) \
+ const struct stm32_dma_cfg DMA ## dma ## _channel ## ch ## _spi ## spi_num
## _tx = { \
+ DMA ## dma ## _CH ## ch, \
+ DMA ## dma ## _Channel ## ch ## _IRQn, \
+ irq_handler, \
+ .regs = DMA ## dma ## _Channel ## ch, \
+ .init = { \
+ .Request = DMA_REQUEST_SPI ## spi_num ## _TX, \
+ .Direction = DMA_MEMORY_TO_PERIPH, \
+ .PeriphInc = DMA_PINC_DISABLE, \
+ .MemInc = DMA_MINC_ENABLE, \
+ .PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
+ .MemDataAlignment = DMA_MDATAALIGN_BYTE, \
+ .Mode = DMA_NORMAL, \
+ .Priority = DMA_PRIORITY_LOW, \
+ } \
+ }
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 1, stm32_dma1_1_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 1, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 1, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 1, stm32_dma1_4_5_6_7_irq_handler);
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 2, stm32_dma1_1_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 2, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 2, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 2, stm32_dma1_4_5_6_7_irq_handler);
+
+SPI_DMA_RX_CHANNEL_DEFINE(1, 1, 3, stm32_dma1_1_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 2, 3, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 3, 3, stm32_dma1_2_3_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 4, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 5, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 6, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_RX_CHANNEL_DEFINE(1, 7, 3, stm32_dma1_4_5_6_7_irq_handler);
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 1, stm32_dma1_1_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 1, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 1, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 1, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 1, stm32_dma1_4_5_6_7_irq_handler);
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 2, stm32_dma1_1_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 2, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 2, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 2, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 2, stm32_dma1_4_5_6_7_irq_handler);
+
+SPI_DMA_TX_CHANNEL_DEFINE(1, 1, 3, stm32_dma1_1_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 2, 3, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 3, 3, stm32_dma1_2_3_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 4, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 5, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 6, 3, stm32_dma1_4_5_6_7_irq_handler);
+SPI_DMA_TX_CHANNEL_DEFINE(1, 7, 3, stm32_dma1_4_5_6_7_irq_handler);
diff --git a/hw/bus/drivers/spi_stm32/stm32g0xx/syscfg.yml
b/hw/bus/drivers/spi_stm32/stm32g0xx/syscfg.yml
new file mode 100644
index 000000000..f1eaafa49
--- /dev/null
+++ b/hw/bus/drivers/spi_stm32/stm32g0xx/syscfg.yml
@@ -0,0 +1,66 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ SPI1_DMA_PRIORITY:
+ description: 'DMA priority for SPI1 RX and TX'
+ value: DMA_PRIORITY_LOW
+ SPI2_DMA_PRIORITY:
+ description: 'DMA priority for SPI2 RX and TX'
+ value: DMA_PRIORITY_LOW
+
+ SPI1_RX_DMA:
+ description: >
+ DMA channel to use for SPI1. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel1_spi1_rx
+ SPI1_TX_DMA:
+ description: >
+ DMA channel to use for SPI1. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel2_spi1_tx
+ SPI2_RX_DMA:
+ description: >
+ DMA channel to use for SPI2. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel3_spi2_rx
+ SPI2_TX_DMA:
+ description: >
+ DMA channel to use for SPI2. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel4_spi2_tx
+ SPI3_RX_DMA:
+ description: >
+ DMA channel to use for SPI3. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel1_spi3_rx
+ SPI3_TX_DMA:
+ description: >
+ DMA channel to use for SPI3. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel2_spi3_tx
+ SPI4_RX_DMA:
+ description: >
+ DMA channel to use for SPI4. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel3_spi4_rx
+ SPI4_TX_DMA:
+ description: >
+ DMA channel to use for SPI4. DMA number can be 1 or 2.
+ channel can be 1-7.
+ value: DMA1_channel4_spi4_tx
