This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new 9d887036e hw/bsp: Add support for WeAct STM32G431 board
9d887036e is described below
commit 9d887036e64c99f08a322fdfbb8e3918bac4d62d
Author: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
AuthorDate: Fri Apr 26 13:27:57 2024 +0200
hw/bsp: Add support for WeAct STM32G431 board
This adds support for chip STM32G431 board with just
one area for bootloader.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenb...@codecoup.pl>
---
.github/test_build_bootloader.sh | 3 +-
.style_ignored_dirs | 1 +
LICENSE | 1 +
hw/bsp/weact_g431cb/bsp.yml | 47 +++
hw/bsp/weact_g431cb/debug.sh | 34 ++
hw/bsp/weact_g431cb/include/bsp/bsp.h | 55 +++
.../weact_g431cb/include/bsp/stm32g4xx_hal_conf.h | 381 +++++++++++++++++++++
hw/bsp/weact_g431cb/link/include/bsp_config.ld.h | 22 ++
hw/bsp/weact_g431cb/pkg.yml | 37 ++
hw/bsp/weact_g431cb/src/hal_bsp.c | 207 +++++++++++
hw/bsp/weact_g431cb/syscfg.yml | 82 +++++
11 files changed, 869 insertions(+), 1 deletion(-)
diff --git a/.github/test_build_bootloader.sh b/.github/test_build_bootloader.sh
index 59e59790c..8389a7a9f 100644
--- a/.github/test_build_bootloader.sh
+++ b/.github/test_build_bootloader.sh
@@ -23,7 +23,8 @@ BSPS=$(ls repos/apache-mynewt-core/hw/bsp)
IGNORED_BSPS="ci40 dialog_cmac embarc_emsk hifive1 native native-armv7\
native-mips nucleo-f030r8 nucleo-f072rb\
olimex-p103 olimex-pic32-emz64 olimex-pic32-hmz144\
- pic32mx470_6lp_clicker pic32mz2048_wi-fire usbmkw41z"
+ pic32mx470_6lp_clicker pic32mz2048_wi-fire usbmkw41z\
+ weact_g431cb"
BSP_COUNT=0
diff --git a/.style_ignored_dirs b/.style_ignored_dirs
index 28bbb59f4..d2f32bc77 100644
--- a/.style_ignored_dirs
+++ b/.style_ignored_dirs
@@ -44,6 +44,7 @@ hw/bsp/stm32f4discovery/include/bsp/stm32f4xx_hal_conf.h
hw/bsp/stm32f7discovery/include/bsp/stm32f7xx_hal_conf.h
hw/bsp/stm32l152discovery/include/bsp/stm32l1xx_hal_conf.h
hw/bsp/nucleo-u575zi-q/include/bsp/stm32u5xx_hal_conf.h
+hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c
hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c
hw/mcu/stm/stm32u5xx/src/system_stm32u5xx.c
diff --git a/LICENSE b/LICENSE
index 3a3706971..76e463a3b 100644
--- a/LICENSE
+++ b/LICENSE
@@ -302,6 +302,7 @@ This product bundles parts of STM32CubeF4 1.5, which is
available under the
* hw/bsp/nucleo-f439zi/include/bsp/stm32f4xx_hal_conf.h
* hw/bsp/stm32f411discovery/include/bsp/stm32f4xx_hal_conf.h
* hw/bsp/stm32f429discovery/include/bsp/stm32f4xx_hal_conf.h
+ * hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
This product bundles parts of STM32CubeF7, which is available under the
"3-clause BSD" license. Bundled files are:
diff --git a/hw/bsp/weact_g431cb/bsp.yml b/hw/bsp/weact_g431cb/bsp.yml
new file mode 100644
index 000000000..62b503f9e
--- /dev/null
+++ b/hw/bsp/weact_g431cb/bsp.yml
@@ -0,0 +1,47 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.name: "WeAct_G431CB"
+bsp.url: https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard
+bsp.maker: "WeActStudio"
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript: autogenerated
+bsp.downloadscript: "hw/scripts/download.sh"
+bsp.debugscript: "hw/bsp/weact_g431cb/debug.sh"
+
+bsp.flash_map:
+ areas:
+ # Only one flash area for code
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 96kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x08018000
+ size: 32kB
+ # Empty flash area to allow build
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08020000
+ size: 0kB
+
+
diff --git a/hw/bsp/weact_g431cb/debug.sh b/hw/bsp/weact_g431cb/debug.sh
new file mode 100644
index 000000000..8445f238e
--- /dev/null
+++ b/hw/bsp/weact_g431cb/debug.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/stlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+stlink_debug
diff --git a/hw/bsp/weact_g431cb/include/bsp/bsp.h
b/hw/bsp/weact_g431cb/include/bsp/bsp.h
new file mode 100644
index 000000000..ab27fc35d
--- /dev/null
+++ b/hw/bsp/weact_g431cb/include/bsp/bsp.h
@@ -0,0 +1,55 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start[];
+
+#define RAM_SIZE (SRAM1_SIZE_MAX + SRAM2_SIZE + CCMSRAM_SIZE)
+
+/* LED pins */
+#define LED_1 MCU_GPIO_PORTC(6)
+
+#define LED_GREEN LED_1
+
+#define LED_BLINK_PIN LED_1
+
+/* Button pin */
+#define BUTTON_1 MCU_GPIO_PORTC(13)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
diff --git a/hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
b/hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
new file mode 100644
index 000000000..913aadb88
--- /dev/null
+++ b/hw/bsp/weact_g431cb/include/bsp/stm32g4xx_hal_conf.h
@@ -0,0 +1,381 @@
+/**
+
******************************************************************************
+ * @file stm32g4xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32g4xx_hal_conf.h.
+
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+
******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion
-------------------------------------*/
+#ifndef STM32G4xx_HAL_CONF_H
+#define STM32G4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <syscfg/syscfg.h>
+
+/* Exported types
------------------------------------------------------------*/
+/* Exported constants
--------------------------------------------------------*/
+
+/* ########################## Module Selection ##############################
*/
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORDIC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_FMAC_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection
############################## */
+/**
+ * @brief This is the list of modules where register callback can be used
+ */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
+#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
+
+/* ########################## Oscillator Values adaptation
####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in
your application.
+ * This value is used by the RCC HAL module to compute the system
frequency
+ * (when HSE is used as system clock source, directly or through the
PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000UL /*!< Value of the External oscillator
in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms
*/
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system
frequency
+ * (when HSI is used as system clock source, directly or through the
PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
+ * This internal oscillator is mainly dedicated to provide a high
precision clock to
+ * the USB peripheral by means of a special Clock Recovery System
(CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it
default frequency
+ * which is subject to manufacturing process variations.
+ */
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed
oscillator for USB FS/RNG in Hz.
+ The real value my vary
depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+/*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations in voltage and
temperature.*/
+#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the
system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms
*/
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S and SAI peripherals
+ * This value is used by the I2S and SAI HAL modules to compute the
I2S and SAI clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE (48000UL) /*!< Value of the External clock
source in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor.
*/
+
+/* ########################### System Configuration #########################
*/
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ##############################
*/
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## SPI peripheral configuration ##########################
*/
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC 1U
+
+/* Includes
------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32g4xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g4xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32g4xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32g4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32g4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32g4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32g4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32g4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32g4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro
------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t
*)__FILE__, __LINE__))
+/* Exported functions -------------------------------------------------------
*/
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_CONF_H */
+
+
diff --git a/hw/bsp/weact_g431cb/link/include/bsp_config.ld.h
b/hw/bsp/weact_g431cb/link/include/bsp_config.ld.h
new file mode 100644
index 000000000..76e485ea4
--- /dev/null
+++ b/hw/bsp/weact_g431cb/link/include/bsp_config.ld.h
@@ -0,0 +1,22 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef IMAGE
+#define IMAGE BOOT
+#endif
diff --git a/hw/bsp/weact_g431cb/pkg.yml b/hw/bsp/weact_g431cb/pkg.yml
new file mode 100644
index 000000000..d3a74c2f9
--- /dev/null
+++ b/hw/bsp/weact_g431cb/pkg.yml
@@ -0,0 +1,37 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/weact_g431cb
+pkg.type: bsp
+pkg.description: BSP definition for the WeAct_g431cb board.
+pkg.author: "Apache Mynewt <d...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/";
+pkg.keywords:
+ - stm32
+ - stm32g4
+
+pkg.cflags: -DSTM32G431xx -DUSE_FULL_LL_DRIVER
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/stm/stm32g4xx"
+ - "@apache-mynewt-core/libc"
+ - "@apache-mynewt-core/hw/scripts"
diff --git a/hw/bsp/weact_g431cb/src/hal_bsp.c
b/hw/bsp/weact_g431cb/src/hal_bsp.c
new file mode 100644
index 000000000..826f462fb
--- /dev/null
+++ b/hw/bsp/weact_g431cb/src/hal_bsp.c
@@ -0,0 +1,207 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "bsp/bsp.h"
+#include "os/mynewt.h"
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_system.h>
+
+#include <stm32g4xx.h>
+#include <stm32_common/stm32_hal.h>
+#if MYNEWT_PKG_apache_mynewt_core__bus_drivers
+#include <bus/drivers/spi_common.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2)
+#include <pwm_stm32/pwm_stm32.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+struct stm32_pwm_conf os_bsp_pwm0_cfg = {
+ .tim = TIM3,
+ .irq = TIM3_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_1)
+struct stm32_pwm_conf os_bsp_pwm1_cfg = {
+ .tim = TIM4,
+ .irq = TIM4_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_2)
+struct stm32_pwm_conf os_bsp_pwm2_cfg = {
+ .tim = TIM1,
+ .irq = TIM1_CC_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_0)
+const struct stm32_uart_cfg os_bsp_uart0_cfg = {
+ .suc_uart = USART1,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB2ENR_USART1EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART1,
+ .suc_irqn = USART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1ENR1,
+ .suc_rcc_dev = RCC_APB1ENR1_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+/*
+ * The PB8 and PB9 pins are connected through jumpers in the board to
+ * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need
+ * to be removed (they are the default connections) and SB138/SB143 need
+ * to be shorted.
+ */
+const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C1EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C1,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C2,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C3,
+ .hic_10bit = 0,
+ .hic_speed = 100000, /* 100kHz */
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE,
+ },
+};
+
+extern const struct hal_flash stm32_flash_dev;
+
+static const struct hal_flash *flash_devs[] = {
+ [0] = &stm32_flash_dev,
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ if (id >= ARRAY_SIZE(flash_devs)) {
+ return NULL;
+ }
+
+ return flash_devs[id];
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+ (void)rc;
+
+ stm32_periph_create();
+}
+
+void
+hal_bsp_deinit(void)
+{
+ RCC->AHB1ENR = 0x00000100;
+ RCC->AHB2ENR = 0x00000000;
+ RCC->AHB3ENR = 0x80000000;
+ RCC->APB1ENR1 = 0x00000400;
+ RCC->APB1ENR2 = 0;
+ RCC->APB2ENR = 0;
+
+ RCC->AHB1RSTR = 0x0000111F;
+ RCC->AHB2RSTR = 0x050F607F;
+ RCC->AHB3RSTR = 0x00000101;
+ RCC->APB1RSTR1 = 0xD2FECD2F;
+ RCC->APB1RSTR2 = 0x00800103;
+ RCC->APB2RSTR = 0x0437F801;
+ RCC->AHB1RSTR = 0;
+ RCC->AHB2RSTR = 0;
+ RCC->AHB3RSTR = 0;
+ RCC->APB1RSTR1 = 0;
+ RCC->APB1RSTR2 = 0;
+ RCC->APB2RSTR = 0;
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
diff --git a/hw/bsp/weact_g431cb/syscfg.yml b/hw/bsp/weact_g431cb/syscfg.yml
new file mode 100644
index 000000000..560731099
--- /dev/null
+++ b/hw/bsp/weact_g431cb/syscfg.yml
@@ -0,0 +1,82 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ STM32_FLASH_SIZE_KB:
+ description: 'Total flash size in KB.'
+ value: 128
+
+ BSP_FLASH_SPI_BUS:
+ description: 'bus name SPIFLASH is connected to'
+ value: '"spi0"'
+
+ BSP_FLASH_SPI_NAME:
+ description: 'SPIFLASH device name'
+ value: '"spiflash0"'
+
+ BOOT_LOADER:
+ description: 'Build everything as bootloader'
+ value: 1
+syscfg.vals:
+ MCU_RAM_START: 0x20000000
+ MCU_RAM_SIZE: 0x8000
+ STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_PLLM: 2
+ STM32_CLOCK_PLL_PLLN: 85
+ STM32_CLOCK_PLL_PLLP: 2
+ STM32_CLOCK_PLL_PLLQ: 2
+ STM32_CLOCK_PLL_PLLR: 2
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
+ UART_0_PIN_TX: 'MCU_GPIO_PORTA(9)'
+ UART_0_PIN_RX: 'MCU_GPIO_PORTA(10)'
+ UART_1_PIN_TX: 'MCU_GPIO_PORTA(2)'
+ UART_1_PIN_RX: 'MCU_GPIO_PORTA(3)'
+ UART_1_PIN_RTS: -1
+ UART_1_PIN_CTS: -1
+ UART_0: 0
+ UART_1: 0
+ SPI_0_PIN_SS: 'MCU_GPIO_PORTD(14)'
+ SPI_0_PIN_SCK: ARDUINO_PIN_SCK
+ SPI_0_PIN_MISO: ARDUINO_PIN_MISO
+ SPI_0_PIN_MOSI: ARDUINO_PIN_MOSI
+ I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)'
+ I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)'
+ I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)'
+ I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)'
+ I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)'
+ I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)'
+ I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)'
+ I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)'
+ TIMER_0_TIM: 'TIM15'
+ TIMER_1_TIM: 'TIM16'
+ TIMER_2_TIM: 'TIM17'
+ BOOTUTIL_SINGLE_APPLICATION_SLOT: 1
+ BOOTUTIL_OVERWRITE_ONLY: 1
+ MYNEWT_DOWNLOADER: stm32_programmer_cli
+ MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x00000000
+ JLINK_TARGET: STM32G431CB
