This is an automated email from the ASF dual-hosted git repository. jerzy pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit f7b01a82390b94c8603325a885465b88e72e041b Author: Jerzy Kasenberg <[email protected]> AuthorDate: Thu Feb 27 12:51:30 2025 +0100 hw/bsp: Add support for blackpill411ce This adds bsp for popular baord from WeActStudio. Board can be equipped with 64Mb flash, If external flash is not present, set SPIFLASH8M to 0. bsp show usage of flash map with two variants depending whether external spi flash is present or not. Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/bsp/blackpill411ce/bsp.yml | 96 ++++++ hw/bsp/blackpill411ce/debug.sh | 34 ++ hw/bsp/blackpill411ce/include/bsp/bsp.h | 51 +++ .../include/bsp/stm32f4xx_hal_conf.h | 370 +++++++++++++++++++++ hw/bsp/blackpill411ce/pkg.yml | 42 +++ hw/bsp/blackpill411ce/src/hal_bsp.c | 220 ++++++++++++ hw/bsp/blackpill411ce/syscfg.yml | 77 +++++ 7 files changed, 890 insertions(+) diff --git a/hw/bsp/blackpill411ce/bsp.yml b/hw/bsp/blackpill411ce/bsp.yml new file mode 100644 index 000000000..4c19ceb12 --- /dev/null +++ b/hw/bsp/blackpill411ce/bsp.yml @@ -0,0 +1,96 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.name: "blackpill411ce" +bsp.url: https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 +bsp.maker: WeAct +bsp.arch: cortex_m4 +bsp.compiler: "@apache-mynewt-core/compiler/arm-none-eabi-m4" +bsp.linkerscript: autogenerated +bsp.downloadscript: "hw/scripts/download.sh" +bsp.debugscript: "hw/bsp/blackpill411ce/debug.sh" + +bsp.flash_map: + areas: + # System areas. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x08000000 + size: 32kB + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x08020000 + size: 374kB + FLASH_AREA_IMAGE_SCRATCH: + device: 1 + offset: 0x08040000 + size: 0kB + FLASH_AREA_REBOOT_LOG: + user_id: 2 + device: 0 + offset: 0x08010000 + size: 64kB + + FLASH_AREA_LITTLEFS: + user_id: 3 + device: 0 + offset: 0x08008000 + size: 32kB + +bsp.flash_map.SPIFLASH8M: + areas: + # Embedded flash 512kB + # Boot loader 32kB. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x08000000 + size: 32kB + # 32kB not allocated + # 64kB reboot log + FLASH_AREA_REBOOT_LOG: + user_id: 2 + device: 0 + offset: 0x08010000 + size: 64kB + # Slot 0 374kB (3*128kB) + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x08020000 + size: 374kB + # SPIFlash 8Mb + # Image scratch 128Kb + FLASH_AREA_IMAGE_SCRATCH: + device: 1 + offset: 0x00000000 + size: 128kB + FLASH_AREA_IMAGE_1: + device: 1 + offset: 0x00020000 + size: 374kB + + FLASH_AREA_NFFS: + user_id: 1 + device: 1 + offset: 0x00080000 + size: 128kB + FLASH_AREA_LITTLEFS: + user_id: 3 + device: 1 + offset: 0x000A0000 + size: 128kB diff --git a/hw/bsp/blackpill411ce/debug.sh b/hw/bsp/blackpill411ce/debug.sh new file mode 100755 index 000000000..d1e28d76a --- /dev/null +++ b/hw/bsp/blackpill411ce/debug.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# Called with following variables set: +# - CORE_PATH is absolute path to @apache-mynewt-core +# - BSP_PATH is absolute path to hw/bsp/bsp_name +# - BIN_BASENAME is the path to prefix to target binary, +# .elf appended to name is the ELF file +# - FEATURES holds the target features string +# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software +# - RESET set if target should be reset when attaching +# - NO_GDB set if we should not start gdb to debug + +. $CORE_PATH/hw/scripts/stlink.sh + +FILE_NAME=$BIN_BASENAME.elf + +stlink_debug diff --git a/hw/bsp/blackpill411ce/include/bsp/bsp.h b/hw/bsp/blackpill411ce/include/bsp/bsp.h new file mode 100644 index 000000000..bafe2ba7b --- /dev/null +++ b/hw/bsp/blackpill411ce/include/bsp/bsp.h @@ -0,0 +1,51 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include <inttypes.h> +#include <mcu/mcu.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define special stackos sections */ +#define sec_data_core __attribute__((section(".data.core"))) +#define sec_bss_core __attribute__((section(".bss.core"))) +#define sec_bss_nz_core __attribute__((section(".bss.core.nz"))) + +/* More convenient section placement macros. */ +#define bssnz_t sec_bss_nz_core + +extern uint8_t _ram_start; + +#define RAM_SIZE (128 * 1024) + +/* LED pins */ +#define LED_BLINK_PIN MCU_GPIO_PORTC(13) + +/* Button pin */ +#define BUTTON_1 MCU_GPIO_PORTA(0) + +#ifdef __cplusplus +} +#endif + +#endif /* H_BSP_H */ diff --git a/hw/bsp/blackpill411ce/include/bsp/stm32f4xx_hal_conf.h b/hw/bsp/blackpill411ce/include/bsp/stm32f4xx_hal_conf.h new file mode 100644 index 000000000..69d471766 --- /dev/null +++ b/hw/bsp/blackpill411ce/include/bsp/stm32f4xx_hal_conf.h @@ -0,0 +1,370 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @author MCD Application Team + * @version V1.2.4 + * @date 06-May-2016 + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#include <syscfg/syscfg.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#if 0 +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +/* #define HAL_SDRAM_MODULE_ENABLED */ +#define HAL_HASH_MODULE_ENABLED +/* #define HAL_GPIO_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#else +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#endif + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if defined (MYNEWT_VAL_STM32_CLOCK_HSE_VALUE) +#define HSE_VALUE MYNEWT_VAL(STM32_CLOCK_HSE_VALUE) +#elif !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE) +#define INSTRUCTION_CACHE_ENABLE MYNEWT_VAL(STM32_INSTRUCTION_CACHE_ENABLE) +#define DATA_CACHE_ENABLE MYNEWT_VAL(STM32_DATA_CACHE_ENABLE) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/blackpill411ce/pkg.yml b/hw/bsp/blackpill411ce/pkg.yml new file mode 100644 index 000000000..3e7ad6104 --- /dev/null +++ b/hw/bsp/blackpill411ce/pkg.yml @@ -0,0 +1,42 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/bsp/blackpill411ce +pkg.type: bsp +pkg.description: BSP definition for the stm32f4 blackpill411ce board. +pkg.author: "Apache Mynewt <[email protected]>" +pkg.homepage: "http://mynewt.apache.org/"; +pkg.keywords: + - stm32 + - stm32f4 + - f411ce + - stm32f411ce + +pkg.cflags: + -DSTM32F411xE + +pkg.cflags.HARDFLOAT: + - -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +pkg.deps: + - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx" + - "@apache-mynewt-core/libc" + - "@apache-mynewt-core/hw/drivers/flash/spiflash" + - "@apache-mynewt-core/hw/scripts" + - "@apache-mynewt-core/boot/startup" diff --git a/hw/bsp/blackpill411ce/src/hal_bsp.c b/hw/bsp/blackpill411ce/src/hal_bsp.c new file mode 100644 index 000000000..e0d3322f0 --- /dev/null +++ b/hw/bsp/blackpill411ce/src/hal_bsp.c @@ -0,0 +1,220 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "mynewt_cm.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32f411xe.h> +#include <stm32_common/stm32_hal.h> + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(ADC_0) || MYNEWT_VAL(ADC_1) || MYNEWT_VAL(ADC_2) +#include "stm32f4xx_hal_adc.h" +#include "adc_stm32f4/adc_stm32f4.h" +#endif + +#if MYNEWT_VAL(SPIFLASH) +#include <spiflash/spiflash.h> +#endif + +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 16kB */ + 0x08004000, /* 16kB */ + 0x08008000, /* 16kB */ + 0x0800c000, /* 16kB */ + 0x08010000, /* 64kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 128kB */ + 0x08060000, /* 128kB */ + 0x08080000, /* End of flash */ +}; + +#define SZ ARRAY_SIZE(stm32_flash_sectors) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART2, + .suc_rcc_reg = &RCC->APB1ENR, + .suc_rcc_dev = RCC_APB1ENR_USART2EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART2, + .suc_irqn = USART2_IRQn, +}; +#endif + +#if MYNEWT_VAL(UART_1) +const struct stm32_uart_cfg os_bsp_uart1_cfg = { + .suc_uart = USART1, + .suc_rcc_reg = &RCC->APB2ENR, + .suc_rcc_dev = RCC_APB2ENR_USART1EN, + .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART1, + .suc_irqn = USART1_IRQn, +}; +#endif + +#if MYNEWT_VAL(UART_2) +const struct stm32_uart_cfg os_bsp_uart2_cfg = { + .suc_uart = USART6, + .suc_rcc_reg = &RCC->APB2ENR, + .suc_rcc_dev = RCC_APB2ENR_USART6EN, + .suc_pin_tx = MYNEWT_VAL(UART_2_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_2_PIN_RX), + .suc_pin_rts = -1, + .suc_pin_cts = -1, + .suc_pin_af = GPIO_AF8_USART6, + .suc_irqn = USART6_IRQn, +}; +#endif + +static const struct hal_bsp_mem_dump dump_cfg[] = { + [0] = { + .hbmd_start = &_ram_start, + .hbmd_size = RAM_SIZE + } +}; + +extern const struct hal_flash stm32_flash_dev; + +#if MYNEWT_VAL(I2C_0) +/* + * NOTE: The PB8 and PB9 pins are connected through jumpers in the board to + * both AIN and I2C pins. To enable I2C functionality SB51/SB56 need to + * be removed (they are the default connections) and SB46/SB52 need to + * be added. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_speed = 100000, /* 100kHz */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_speed = 100000, +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C3EN, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_speed = 100000, +}; +#endif + +static const struct hal_flash *flash_devs[] = { + [0] = &stm32_flash_dev, +#if MYNEWT_VAL(SPIFLASH) + [1] = &spiflash_dev.hal, +#endif +}; + +const struct hal_flash * +hal_bsp_flash_dev(uint8_t id) +{ + if (id >= ARRAY_SIZE(flash_devs)) { + return NULL; + } + + return flash_devs[id]; +} + +const struct hal_bsp_mem_dump * +hal_bsp_core_dump(int *area_cnt) +{ + *area_cnt = ARRAY_SIZE(dump_cfg); + return dump_cfg; +} + +void +hal_bsp_init(void) +{ + stm32_periph_create(); +} + +void +hal_bsp_deinit(void) +{ + Cortex_DisableAll(); + + RCC->AHB1ENR = 0; + RCC->AHB2ENR = 0; + RCC->APB1ENR = 0; + RCC->APB2ENR = 0; + RCC->AHB1RSTR = 0x00C0109F; + RCC->AHB2RSTR = 0x00000080; + RCC->APB1RSTR = 0x10E2C80F; + RCC->APB2RSTR = 0x00177931; + RCC->AHB1RSTR = 0x00000000; + RCC->AHB2RSTR = 0x00000000; + RCC->APB1RSTR = 0x00000000; + RCC->APB2RSTR = 0x00000000; +} + +/** + * Returns the configured priority for the given interrupt. If no priority + * configured, return the priority passed in + * + * @param irq_num + * @param pri + * + * @return uint32_t + */ +uint32_t +hal_bsp_get_nvic_priority(int irq_num, uint32_t pri) +{ + /* Add any interrupt priorities configured by the bsp here */ + return pri; +} diff --git a/hw/bsp/blackpill411ce/syscfg.yml b/hw/bsp/blackpill411ce/syscfg.yml new file mode 100644 index 000000000..215c8e0e9 --- /dev/null +++ b/hw/bsp/blackpill411ce/syscfg.yml @@ -0,0 +1,77 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + SPIFLASH8M: + description: Board has 8MB external SPI flash + value: 1 + +syscfg.vals: + STM32_FLASH_SIZE_KB: 512 + STM32_FLASH_NUM_AREAS: 8 + MCU_RAM_START: 0x20000000 + MCU_RAM_SIZE: 0x20000 + BOOTUTIL_SINGLE_APPLICATION_SLOT: 1 + REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG + CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS + NFFS_FLASH_AREA: FLASH_AREA_NFFS + STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1' + STM32_CLOCK_HSI: 0 + STM32_CLOCK_HSE: 1 + STM32_CLOCK_HSE_VALUE: 25000000 + STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_PLL_PLLM: 25 + STM32_CLOCK_PLL_PLLN: 192 + STM32_CLOCK_PLL_PLLP: 2 + STM32_CLOCK_PLL_PLLQ: 4 + STM32_CLOCK_ENABLE_OVERDRIVE: 0 + STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1' + STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV2' + STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1' + STM32_FLASH_LATENCY: 'FLASH_LATENCY_3' + STM32_FLASH_PREFETCH_ENABLE: 1 + STM32_INSTRUCTION_CACHE_ENABLE: 1 + STM32_DATA_CACHE_ENABLE: 1 + WATCHDOG_INTERVAL: 28000 + UART_0_PIN_TX: 'MCU_GPIO_PORTA(2)' + UART_0_PIN_RX: 'MCU_GPIO_PORTA(3)' + UART_1_PIN_TX: 'MCU_GPIO_PORTA(9)' + UART_1_PIN_RX: 'MCU_GPIO_PORTA(10)' + SPI_0_PIN_SS: 'MCU_GPIO_PORTA(4)' + SPI_0_PIN_SCK: 'MCU_GPIO_PORTA(5)' + SPI_0_PIN_MISO: 'MCU_GPIO_PORTA(6)' + SPI_0_PIN_MOSI: 'MCU_GPIO_PORTA(7)' + I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)' + I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)' + I2C_1_PIN_SCL: 'MCU_GPIO_PORTB(10)' + I2C_1_PIN_SDA: 'MCU_GPIO_PORTB(11)' + I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)' + I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)' + TIMER_0_TIM: 'TIM9' + SPIFLASH_SECTOR_COUNT: 1024 + SPIFLASH_SECTOR_SIZE: 4096 + SPIFLASH_PAGE_SIZE: 256 + MYNEWT_DOWNLOADER: stm32_programmer_cli + MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x08000000 + PYOCD_TARGET: stm32f412xe + JLINK_TARGET: STM32F411CE + +syscfg.vals.SPIFLASH8M: + BOOTUTIL_SINGLE_APPLICATION_SLOT: 0 + COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
