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jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new 2c284c205 hw/stm32u5: Fix clock settings
2c284c205 is described below
commit 2c284c205bdde0ccdfaf239e1d612c05fbde852e
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Mon Mar 31 09:26:21 2025 +0200
hw/stm32u5: Fix clock settings
Few minor changes:
- U5 does not have APB4 bus (settings removed from BSP)
- ABP3 presacler was now configurable in syscfg
- STM32_CLOCK_ENABLE_OVERDRIVE is not applicable fot U5
- descriptions of AHB and APB syscfg was incorrect
- PLLREG was not configurable even though BSP had some
inactive setting
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/bsp/nucleo-u575zi-q/syscfg.yml | 4 +---
hw/mcu/stm/stm32u5xx/src/clock_stm32u5xx.c | 7 +++++++
hw/mcu/stm/stm32u5xx/syscfg.yml | 14 +++++++++++---
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/hw/bsp/nucleo-u575zi-q/syscfg.yml
b/hw/bsp/nucleo-u575zi-q/syscfg.yml
index 493bc07b2..513e779db 100644
--- a/hw/bsp/nucleo-u575zi-q/syscfg.yml
+++ b/hw/bsp/nucleo-u575zi-q/syscfg.yml
@@ -32,13 +32,11 @@ syscfg.vals:
STM32_CLOCK_PLL_PLLP: 2
STM32_CLOCK_PLL_PLLQ: 2
STM32_CLOCK_PLL_PLLR: 2
- STM32_CLOCK_ENABLE_OVERDRIVE: 0
+ STM32_CLOCK_PLL_PLLRGE: 'RCC_PLLVCIRANGE_0'
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
WATCHDOG_INTERVAL: 28000
UART_0_PIN_TX: 'MCU_GPIO_PORTA(9)'
diff --git a/hw/mcu/stm/stm32u5xx/src/clock_stm32u5xx.c
b/hw/mcu/stm/stm32u5xx/src/clock_stm32u5xx.c
index 106107a6e..e0ab416c6 100644
--- a/hw/mcu/stm/stm32u5xx/src/clock_stm32u5xx.c
+++ b/hw/mcu/stm/stm32u5xx/src/clock_stm32u5xx.c
@@ -207,6 +207,8 @@ SystemClock_Config(void)
osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP);
osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ);
osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR);
+ osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLL_PLLRGE);
+
if (MYNEWT_VAL(STM32_CLOCK_PLL_BOOST_DIV) >= 0) {
osc_init.PLL.PLLMBOOST = MYNEWT_VAL(STM32_CLOCK_PLL_BOOST_DIV);
}
@@ -235,11 +237,16 @@ SystemClock_Config(void)
#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER))
#error "APB2 clock divider is invalid"
+#endif
+
+#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB3_DIVIDER))
+#error "APB2 clock divider is invalid"
#endif
clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER);
clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER);
clk_init.APB2CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER);
+ clk_init.APB3CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB3_DIVIDER);
#if !IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY))
#error "Flash latency value is invalid"
diff --git a/hw/mcu/stm/stm32u5xx/syscfg.yml b/hw/mcu/stm/stm32u5xx/syscfg.yml
index daff5106f..38ea532d9 100644
--- a/hw/mcu/stm/stm32u5xx/syscfg.yml
+++ b/hw/mcu/stm/stm32u5xx/syscfg.yml
@@ -99,6 +99,10 @@ syscfg.defs:
description: PLL config R parameter
value: 0
+ STM32_CLOCK_PLL_PLLRGE:
+ description: PLL input frequency range
+ value: RCC_PLLVCIRANGE_0
+
STM32_CLOCK_PLL_BOOST_DIV:
description: >
Divider for PLL boost required when target SYSCLK > 55MHz.
@@ -108,15 +112,19 @@ syscfg.defs:
value: RCC_PLLMBOOST_DIV1
STM32_CLOCK_AHB_DIVIDER:
- description: AHB CLK1 prescaler (80MHz max)
+ description: AHB CLK1 prescaler (AHB 160MHz max)
value: 0
STM32_CLOCK_APB1_DIVIDER:
- description: APB low-speed prescaler (80MHz max)
+ description: APB prescaler (APB1 160MHz max)
value: 0
STM32_CLOCK_APB2_DIVIDER:
- description: APB high-speed prescaler (80MHz max)
+ description: APB prescaler (APB2 160MHz max)
+ value: 0
+
+ STM32_CLOCK_APB3_DIVIDER:
+ description: APB prescaler (APB3 160MHz max)
value: 0
STM32_FLASH_LATENCY:
