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commit cc7583a86e30a45716993cfffd309eb682fe6ddc Author: Jerzy Kasenberg <[email protected]> AuthorDate: Mon Jun 29 15:05:03 2026 +0200 bsp/stm32fdiscovery: Add QSPI supprt Changes: - corrects flash map of stm32f7discovery (adds QSPI) - adds constant for peripheral pins Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/bsp/stm32f7discovery/bsp.yml | 19 +++-- hw/bsp/stm32f7discovery/include/bsp/bsp.h | 132 ++++++++++++++++++++++++++++++ hw/bsp/stm32f7discovery/pkg.yml | 1 + hw/bsp/stm32f7discovery/src/hal_bsp.c | 61 +++++++++++++- hw/bsp/stm32f7discovery/syscfg.yml | 17 +++- 5 files changed, 218 insertions(+), 12 deletions(-) diff --git a/hw/bsp/stm32f7discovery/bsp.yml b/hw/bsp/stm32f7discovery/bsp.yml index 82a977c45..0b79ee44d 100644 --- a/hw/bsp/stm32f7discovery/bsp.yml +++ b/hw/bsp/stm32f7discovery/bsp.yml @@ -36,11 +36,11 @@ bsp.flash_map: FLASH_AREA_IMAGE_0: device: 0 offset: 0x08020000 - size: 384kB + size: 768kB FLASH_AREA_IMAGE_1: - device: 0 - offset: 0x08080000 - size: 384kB + device: 1 + offset: 0x90000000 + size: 768kB FLASH_AREA_IMAGE_SCRATCH: device: 0 offset: 0x080E0000 @@ -52,8 +52,13 @@ bsp.flash_map: device: 0 offset: 0x08008000 size: 32kB - FLASH_AREA_NFFS: + FLASH_AREA_LITTLEFS: user_id: 1 - device: 0 - offset: 0x08010000 + device: 1 + offset: 0x900E0000 + size: 64kB + FLASH_AREA_FCB: + user_id: 2 + device: 1 + offset: 0x900F0000 size: 64kB diff --git a/hw/bsp/stm32f7discovery/include/bsp/bsp.h b/hw/bsp/stm32f7discovery/include/bsp/bsp.h index ccf69fb09..6be76bce0 100644 --- a/hw/bsp/stm32f7discovery/include/bsp/bsp.h +++ b/hw/bsp/stm32f7discovery/include/bsp/bsp.h @@ -20,6 +20,7 @@ #define H_BSP_H #include <inttypes.h> +#include <stm32f7xx_hal_gpio_ex.h> #include <mcu/mcu.h> #ifdef __cplusplus @@ -84,6 +85,137 @@ extern uint8_t _ram2_start[]; #define ARDUINO_PIN_MOSI ARDUINO_PIN_D11 #define ARDUINO_PIN_MISO ARDUINO_PIN_D12 +#define LCD_BL_CTRL_PIN MCU_GPIO_PORTK(3) + +#define VCP_TX_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(9), GPIO_AF7_USART1) +#define VCP_RX_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(10), GPIO_AF7_USART1) + +#define uSD_Detect_PIN MCU_GPIO_PORTC(13) +#define SDMMC_CK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(12), GPIO_AF12_SDMMC1) +#define SDMMC_CMD_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(2), GPIO_AF12_SDMMC1) +#define SDMMC_D0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(8), GPIO_AF12_SDMMC1) +#define SDMMC_D1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(9), GPIO_AF12_SDMMC1) +#define SDMMC_D2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(10), HAL_AF12_SDMMC1) +#define SDMMC_D3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(11), HAL_AF12_SDMMC1) + +#define SAI_MCLK_A_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(4), 12) +#define SAI2_SD_B_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(10), 12) +#define SAI2_SCK_A_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(5), 12) +#define SAI2_FS_A_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(7), 12) +#define SAI2_SD_A_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(6), 12) + +#define QUADSPI_CLK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(2), GPIO_AF9_QUADSPI) +#define QUADSPI_BKS_NCS_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(6), GPIO_AF10_QUADSPI) +#define QUADSPI_BK1_IO0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(11), GPIO_AF9_QUADSPI) +#define QUADSPI_BK1_IO1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(12), GPIO_AF9_QUADSPI) +#define QUADSPI_BK1_IO2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(2), GPIO_AF9_QUADSPI) +#define QUADSPI_BK1_IO3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(13), GPIO_AF9_QUADSPI) + +#define OTG_FS_OverCurrent_PIN MCU_GPIO_PORTD(4) +#define USB_OTG_FS_DP_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(12), GPIO_AF12_USB_FS) +#define USB_OTG_FS_DM_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(11), GPIO_AF12_USB_FS) +#define USB_OTG_FS_VBUS_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(12), GPIO_AF12_USB_FS) +#define USB_OTG_FS_ID_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(10), GPIO_AF12_USB_FS) +#define USB_OTG_FS_PowerSwitchON_PIN MCU_GPIO_PORTD(5) + +#define OTG_HS_OverCurrent_PIN MCU_GPIO_PORTE(3) +#define USB_OTG_HS_ULPI_CK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(5), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_STP_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(0), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_NEXT_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTH(4), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_DIR_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(2), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(3), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(0), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(1), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(10), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(11), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(12), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(13), GPIO_AF10_USB_HS) +#define USB_OTG_HS_ULPI_D7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTB(5), GPIO_AF10_USB_HS) + +#define ETH_TX_EN_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(11), GPIO_AF11_ETH) +#define ETH_MDC_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(1), GPIO_AF11_ETH) +#define ETH_MDIO_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(2), GPIO_AF11_ETH) +#define ETH_REF_CLK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(1), GPIO_AF11_ETH) +#define ETH_CRS_DV_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTA(7), GPIO_AF11_ETH) +#define ETH_RXD0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(4), GPIO_AF11_ETH) +#define ETH_RXD1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(5), GPIO_AF11_ETH) +#define ETH_TXD0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(13), GPIO_AF11_ETH) +#define ETH_TXD1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(14), GPIO_AF11_ETH) +#define RMII_RXER_PIN MCU_GPIO_PORTG(14) + +#define I2C3_SCL MCU_AFIO_GPIO(MCU_GPIO_PORTH(7), GPIO_AF4_I2C3) +#define I2C3_SDA MCU_AFIO_GPIO(MCU_GPIO_PORTH(8), GPIO_AF4_I2C3) + +#define FMC_SDNRAS_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(11), GPIO_AF12_FMC) +#define FMC_SDNCAS_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(15), GPIO_AF12_FMC) +#define FMC_SDCLK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(8), GPIO_AF12_FMC) +#define FMC_SDNWE_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTH(5), GPIO_AF12_FMC) +#define FMC_SDNE0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTH(3), GPIO_AF12_FMC) +#define FMC_SDCKE0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTC(3), GPIO_AF12_FMC) +#define FMC_NBL0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(0), GPIO_AF12_FMC) +#define FMC_NBL1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(1), GPIO_AF12_FMC) +#define FMC_NBL2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(), GPIO_AF12_FMC) +#define FMC_A0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(0), GPIO_AF12_FMC) +#define FMC_A1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(1), GPIO_AF12_FMC) +#define FMC_A3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(3), GPIO_AF12_FMC) +#define FMC_A4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(4), GPIO_AF12_FMC) +#define FMC_A5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(5), GPIO_AF12_FMC) +#define FMC_A6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(12), GPIO_AF12_FMC) +#define FMC_A7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(13), GPIO_AF12_FMC) +#define FMC_A8_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(14), GPIO_AF12_FMC) +#define FMC_A9_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTF(15), GPIO_AF12_FMC) +#define FMC_A10_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(0), GPIO_AF12_FMC) +#define FMC_A11_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(1), GPIO_AF12_FMC) +#define FMC_A14_BA0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(4), GPIO_AF12_FMC) +#define FMC_A15_BA1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(5), GPIO_AF12_FMC) +#define FMC_D0_DA0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(14), GPIO_AF12_FMC) +#define FMC_D1_DA1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(15), GPIO_AF12_FMC) +#define FMC_D2_DA2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(0), GPIO_AF12_FMC) +#define FMC_D3_DA3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(1), GPIO_AF12_FMC) +#define FMC_D4_DA4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(7), GPIO_AF12_FMC) +#define FMC_D5_DA5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(8), GPIO_AF12_FMC) +#define FMC_D6_DA6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(9), GPIO_AF12_FMC) +#define FMC_D7_DA7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(10), GPIO_AF12_FMC) +#define FMC_D8_DA8_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(11), GPIO_AF12_FMC) +#define FMC_D11_DA11_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(14), GPIO_AF12_FMC) +#define FMC_D13_DA13_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(8), GPIO_AF12_FMC) +#define FMC_D14_DA14_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(9), GPIO_AF12_FMC) +#define FMC_D15_DA15_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(10), GPIO_AF12_FMC) + +#define LCD_DISP_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(12), GPIO_AF14_LTDC) +#define LTDC_CLK_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(14), GPIO_AF14_LTDC) +#define LTDC_R0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(15), GPIO_AF14_LTDC) +#define LTDC_R1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(0), GPIO_AF14_LTDC) +#define LTDC_R2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(1), GPIO_AF14_LTDC) +#define LTDC_R3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(2), GPIO_AF14_LTDC) +#define LTDC_R4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(3), GPIO_AF14_LTDC) +#define LTDC_R5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(4), GPIO_AF14_LTDC) +#define LTDC_R6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(5), GPIO_AF14_LTDC) +#define LTDC_R7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(6), GPIO_AF14_LTDC) +#define LTDC_G0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(7), GPIO_AF14_LTDC) +#define LTDC_G1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(8), GPIO_AF14_LTDC) +#define LTDC_G2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(9), GPIO_AF14_LTDC) +#define LTDC_G3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(10), GPIO_AF14_LTDC) +#define LTDC_G4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(11), GPIO_AF14_LTDC) +#define LTDC_G5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(0), GPIO_AF14_LTDC) +#define LTDC_G6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(1), GPIO_AF14_LTDC) +#define LTDC_G7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(2), GPIO_AF14_LTDC) +#define LTDC_B0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTE(4), GPIO_AF14_LTDC) +#define LTDC_B1_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(13), GPIO_AF14_LTDC) +#define LTDC_B2_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(14), GPIO_AF14_LTDC) +#define LTDC_B3_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTJ(15), GPIO_AF14_LTDC) +#define LTDC_B4_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTG(12), GPIO_AF14_LTDC) +#define LTDC_B5_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(4), GPIO_AF14_LTDC) +#define LTDC_B6_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(5), GPIO_AF14_LTDC) +#define LTDC_B7_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(6), GPIO_AF14_LTDC) +#define LTDC_DE_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTK(7), GPIO_AF14_LTDC) +#define LTDC_HSYNC_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(10), GPIO_AF14_LTDC) +#define LTDC_VSYNC_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTI(9), GPIO_AF14_LTDC) + +#define SPDIF_RX0_PIN MCU_AFIO_GPIO(MCU_GPIO_PORTD(7), GPIO_AF8_SPDIFRX) + +#define AUDIO_INT_PIN MCU_GPIO_PORTD(6) + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f7discovery/pkg.yml b/hw/bsp/stm32f7discovery/pkg.yml index dfa09cdcd..8f2f3f662 100644 --- a/hw/bsp/stm32f7discovery/pkg.yml +++ b/hw/bsp/stm32f7discovery/pkg.yml @@ -37,3 +37,4 @@ pkg.deps: - "@apache-mynewt-core/libc" - "@apache-mynewt-core/hw/scripts" - "@apache-mynewt-core/boot/startup" + - "@apache-mynewt-core/hw/drivers/flash/stm32_qspi" diff --git a/hw/bsp/stm32f7discovery/src/hal_bsp.c b/hw/bsp/stm32f7discovery/src/hal_bsp.c index 444b36676..f0954f535 100644 --- a/hw/bsp/stm32f7discovery/src/hal_bsp.c +++ b/hw/bsp/stm32f7discovery/src/hal_bsp.c @@ -29,6 +29,10 @@ #include <stm32f746xx.h> #include <stm32_common/stm32_hal.h> +#if MYNEWT_PKG_apache_mynewt_core__hw_drivers_flash_stm32_qspi +#include <stm32_qspi.h> +#endif + #if MYNEWT_VAL(ETH_0) #include <stm32_eth/stm32_eth.h> #include <stm32_eth/stm32_eth_cfg.h> @@ -89,6 +93,51 @@ const struct stm32_uart_cfg os_bsp_uart0_cfg = { }; #endif +#if MYNEWT_VAL(I2C_1) +/* + * NOTE: The PB8 and PB9 pins are connected through jumpers in the board to + * both AIN and I2C pins. To enable I2C functionality SB51/SB56 need to + * be removed (they are the default connections) and SB46/SB52 need to + * be added. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_speed = 100000, +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_speed = 100000, +}; +#endif + +#if MYNEWT_VAL(I2C_3) +const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C3EN, + .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_speed = 100000, +}; +#endif + #if MYNEWT_VAL(ETH_0) const struct stm32_eth_cfg os_bsp_eth0_cfg = { /* @@ -142,10 +191,13 @@ hal_bsp_flash_dev(uint8_t id) /* * Internal flash mapped to id 0. */ - if (id != 0) { - return NULL; + if (id == 0) { + return &stm32_flash_dev; + } + if (id == 1) { + return qspi_flash_0; } - return &stm32_flash_dev; + return NULL; } const struct hal_bsp_mem_dump * @@ -158,6 +210,9 @@ hal_bsp_core_dump(int *area_cnt) void hal_bsp_init(void) { + /* Turn off LCD back light */ + hal_gpio_init_out(LCD_BL_CTRL_PIN, 0); + stm32_periph_create(); } diff --git a/hw/bsp/stm32f7discovery/syscfg.yml b/hw/bsp/stm32f7discovery/syscfg.yml index 72145f081..a158390d4 100644 --- a/hw/bsp/stm32f7discovery/syscfg.yml +++ b/hw/bsp/stm32f7discovery/syscfg.yml @@ -23,8 +23,8 @@ syscfg.vals: MCU_RAM_START: 0x20010000 MCU_RAM_SIZE: 240K REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG - CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS - NFFS_FLASH_AREA: FLASH_AREA_NFFS + CONFIG_FCB_FLASH_AREA: FLASH_AREA_FCB + NFFS_FLASH_AREA: FLASH_AREA_LITTLEFS COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1 STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE2' STM32_CLOCK_HSI: 0 @@ -47,8 +47,21 @@ syscfg.vals: TIMER_0_TIM: 'TIM1' TIMER_1_TIM: 'TIM8' TIMER_2_TIM: 'TIM9' + I2C_1_PIN_SCL: 'MCU_GPIO_PORTB(8)' + I2C_1_PIN_SDA: 'MCU_GPIO_PORTB(9)' + I2C_3_PIN_SCL: 'MCU_GPIO_PORTH(7)' + I2C_3_PIN_SDA: 'MCU_GPIO_PORTH(8)' MYNEWT_DOWNLOADER: openocd MYNEWT_DOWNLOADER_OPENOCD_CFG: stm32f7discovery.cfg MYNEWT_DOWNLOADER_OPENOCD_INTERFACE: interface/stlink.cfg MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x08000000 JLINK_TARGET: STM32F746NG + +syscfg.vals.STM32_QSPI_FLASH: + STM32_QSPI_FLASH_PIN_CS: QUADSPI_BKS_NCS_PIN + STM32_QSPI_FLASH_PIN_SCK: QUADSPI_CLK_PIN + STM32_QSPI_FLASH_PIN_DIO0: QUADSPI_BK1_IO0_PIN + STM32_QSPI_FLASH_PIN_DIO1: QUADSPI_BK1_IO1_PIN + STM32_QSPI_FLASH_PIN_DIO2: QUADSPI_BK1_IO2_PIN + STM32_QSPI_FLASH_PIN_DIO3: QUADSPI_BK1_IO3_PIN + STM32_QSPI_FLASH_SECTOR_COUNT: 2048
