This is an automated email from the ASF dual-hosted git repository. kasjer pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 66da27da7b739cf9d7dd2c54fe0b036a2de3aae2 Author: Jerzy Kasenberg <[email protected]> AuthorDate: Mon Sep 14 15:16:32 2026 +0200 mcu/stm32h5: Update pins and clocks for STM32H503 STM32H503 does not have PLL3 and some other peripherals that most STM32H5 device have. Now more code is excluded for STM32H503 devices. Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h | 58 ++++ hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h | 296 +++++++++++---------- .../tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c | 2 + 3 files changed, 209 insertions(+), 147 deletions(-) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h index 906e0ee5d..95d70c69b 100644 --- a/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h +++ b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h @@ -39,9 +39,15 @@ STM32_PER_CLOCK_DEF(GPIOA); STM32_PER_CLOCK_DEF(GPIOB); STM32_PER_CLOCK_DEF(GPIOC); STM32_PER_CLOCK_DEF(GPIOD); +#ifdef GPIOE STM32_PER_CLOCK_DEF(GPIOE); +#endif +#ifdef GPIOF STM32_PER_CLOCK_DEF(GPIOF); +#endif +#ifdef GPIOG STM32_PER_CLOCK_DEF(GPIOG); +#endif STM32_PER_CLOCK_DEF(GPIOH); #ifdef GPIOI STM32_PER_CLOCK_DEF(GPIOI); @@ -49,9 +55,15 @@ STM32_PER_CLOCK_DEF(GPIOI); STM32_PER_CLOCK_DEF(USART1); STM32_PER_CLOCK_DEF(USART2); STM32_PER_CLOCK_DEF(USART3); +#ifdef UART4 STM32_PER_CLOCK_DEF(UART4); +#endif +#ifdef UART5 STM32_PER_CLOCK_DEF(UART5); +#endif +#ifdef USART6 STM32_PER_CLOCK_DEF(USART6); +#endif #ifdef UART7 STM32_PER_CLOCK_DEF(UART7); #endif @@ -70,7 +82,9 @@ STM32_PER_CLOCK_DEF(USART11); STM32_PER_CLOCK_DEF(SPI1); STM32_PER_CLOCK_DEF(SPI2); STM32_PER_CLOCK_DEF(SPI3); +#ifdef SPI4 STM32_PER_CLOCK_DEF(SPI4); +#endif #ifdef SPI5 STM32_PER_CLOCK_DEF(SPI5); #endif @@ -79,52 +93,66 @@ STM32_PER_CLOCK_DEF(SPI6); #endif STM32_PER_CLOCK_DEF(I2C1); STM32_PER_CLOCK_DEF(I2C2); +#ifdef I2C3 STM32_PER_CLOCK_DEF(I2C3); +#endif #ifdef I2C4 STM32_PER_CLOCK_DEF(I2C4); #endif STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PCLK2); STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL2Q); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL3Q); +#endif STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, HSI); STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, CSI); STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, LSE); STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PCLK1); STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL2Q); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL3Q); +#endif STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, HSI); STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, CSI); STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, LSE); STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PCLK1); STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL2Q); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL3Q); +#endif STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, HSI); STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, CSI); STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, LSE); +#ifdef UART4 STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PCLK1); STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL2Q); STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL3Q); STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, HSI); STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, CSI); STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, LSE); +#endif +#ifdef UART5 STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PCLK1); STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL2Q); STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL3Q); STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, HSI); STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, CSI); STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, LSE); +#endif +#ifdef USART6 STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PCLK1); STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL2Q); STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL3Q); STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, HSI); STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, CSI); STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, LSE); +#endif #ifdef UART7 STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PCLK1); @@ -182,14 +210,18 @@ STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, LSE); STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PCLK3); STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL2P); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSE); STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSI); STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, CLKP); STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PCLK1); STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL2P); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSE); STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSI); STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, CLKP); @@ -233,28 +265,36 @@ STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, CLKP); STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL1Q); STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL2P); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL3P); +#endif STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PIN); STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, CLKP); STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL1Q); STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL2P); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL3P); +#endif STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PIN); STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, CLKP); STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL1Q); STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL2P); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL3P); +#endif STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PIN); STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, CLKP); +#ifdef SPI4 STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PCLK2); STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL2Q); STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL3Q); STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSI); STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, CSI); STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSE); +#endif #ifdef SPI5 STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PCLK3); @@ -276,7 +316,9 @@ STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, HSE); STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PCLK3); STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL2Q); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL3Q); +#endif STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, HSI); STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, CSI); STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, LSE); @@ -286,11 +328,15 @@ STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSI); STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSE); STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL1Q); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL3Q); +#endif STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, HSI48); +#ifdef SDMMC1 STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL1Q); STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL2R); +#endif #ifdef SDMMC2 STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL1Q); @@ -298,19 +344,25 @@ STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL2R); #endif STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PCLK1); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, HSI); STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, CSI); STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PCLK1); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, HSI); STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, CSI); +#ifdef I2C3 STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PCLK3); STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PLL3R); STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, HSI); STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, CSI); +#endif #ifdef I2C4 STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, PCLK3); @@ -320,12 +372,16 @@ STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, CSI); #endif STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PCLK1); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, HSI); #ifdef I3C2 STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PCLK3); +#ifdef RCC_CR_PLL3ON STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PLL3R); +#endif STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, HSI); #endif @@ -341,9 +397,11 @@ STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, PLL1Q); STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSE); STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSI); +#ifdef CEC STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSE); STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSI); STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, CSI_DIV122); +#endif STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, HSE); STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, PLL1Q); diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h index f55237499..31f7d4aea 100644 --- a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h @@ -1664,6 +1664,154 @@ STM32_PIN_FUN_CFG(D, 1, FMC_DA3, GPIO_AF12_FMC) #ifdef UART4 STM32_PIN_FUN_CFG(D, 1, UART4_TX, GPIO_AF8_UART4) #endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 2, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(D, 2, LPTIM4_ETR, GPIO_AF14_LPTIM4) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 2, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(D, 2, SDMMC1_CMD, GPIO_AF12_SDMMC1) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(D, 2, TIM15_BKIN, GPIO_AF4_TIM15) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(D, 2, TIM3_ETR, GPIO_AF2_TIM3) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(D, 2, UART5_RX, GPIO_AF8_UART5) +#endif +#ifndef STM32H5 +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 3, DCMI_D5, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 3, FMC_CLK, GPIO_AF12_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(D, 3, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 3, PSSI_D5, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(D, 3, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 3, USART2_CTS, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 3, USART2_NSS, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 4, FMC_NOE, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 4, OCTOSPI1_IO4, GPIO_AF10_OCTOSPI1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 4, USART2_DE, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 4, USART2_RTS, GPIO_AF7_USART2) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(D, 5, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 5, FMC_NWE, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 5, OCTOSPI1_IO5, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(D, 5, SPI2_RDY, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(D, 5, TIM1_CH4N, GPIO_AF1_TIM1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 5, USART2_TX, GPIO_AF7_USART2) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 6, DCMI_D10, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 6, FMC_NWAIT, GPIO_AF12_FMC) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(D, 6, I2S3_SDO, GPIO_AF5_SPI3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 6, OCTOSPI1_IO6, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 6, PSSI_D10, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 6, SAI1_D1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 6, SAI1_SD_A, GPIO_AF6_SAI1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(D, 6, SDMMC2_CK, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(D, 6, SPI3_MOSI, GPIO_AF5_SPI3) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 6, USART2_RX, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 7, FMC_NCE, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 7, FMC_NE1, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(D, 7, I2S1_SDO, GPIO_AF5_SPI1) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(D, 7, LPTIM4_OUT, GPIO_AF14_LPTIM4) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 7, OCTOSPI1_IO7, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(D, 7, SDMMC2_CMD, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(D, 7, SPI1_MOSI, GPIO_AF5_SPI1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 7, USART2_CK, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 8, FMC_D13, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 8, FMC_DA13, GPIO_AF12_FMC) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 8, USART3_TX, GPIO_AF7_USART3) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(D, 9, FDCAN2_RX, GPIO_AF9_FDCAN2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 9, FMC_D14, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 9, FMC_DA14, GPIO_AF12_FMC) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 9, USART3_RX, GPIO_AF7_USART3) +#endif #ifdef FMC STM32_PIN_FUN_CFG(D, 10, FMC_D15, GPIO_AF12_FMC) #endif @@ -1823,152 +1971,6 @@ STM32_PIN_FUN_CFG(D, 15, UART8_RTS, GPIO_AF8_UART8) #ifdef UART9 STM32_PIN_FUN_CFG(D, 15, UART9_TX, GPIO_AF11_UART9) #endif -#ifdef DCMI -STM32_PIN_FUN_CFG(D, 2, DCMI_D11, GPIO_AF13_DCMI) -#endif -#ifdef LPTIM4 -STM32_PIN_FUN_CFG(D, 2, LPTIM4_ETR, GPIO_AF14_LPTIM4) -#endif -#ifdef PSSI -STM32_PIN_FUN_CFG(D, 2, PSSI_D11, GPIO_AF13_PSSI) -#endif -#ifdef SDMMC1 -STM32_PIN_FUN_CFG(D, 2, SDMMC1_CMD, GPIO_AF12_SDMMC1) -#endif -#ifdef TIM15 -STM32_PIN_FUN_CFG(D, 2, TIM15_BKIN, GPIO_AF4_TIM15) -#endif -#ifdef TIM3 -STM32_PIN_FUN_CFG(D, 2, TIM3_ETR, GPIO_AF2_TIM3) -#endif -#ifdef UART5 -STM32_PIN_FUN_CFG(D, 2, UART5_RX, GPIO_AF8_UART5) -#endif -#ifdef DCMI -STM32_PIN_FUN_CFG(D, 3, DCMI_D5, GPIO_AF13_DCMI) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 3, FMC_CLK, GPIO_AF12_FMC) -#endif -#ifdef I2S2 -STM32_PIN_FUN_CFG(D, 3, I2S2_CK, GPIO_AF5_SPI2) -#endif -#ifdef PSSI -STM32_PIN_FUN_CFG(D, 3, PSSI_D5, GPIO_AF13_PSSI) -#endif -#ifdef SPI2 -STM32_PIN_FUN_CFG(D, 3, SPI2_SCK, GPIO_AF5_SPI2) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 3, USART2_CTS, GPIO_AF7_USART2) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 3, USART2_NSS, GPIO_AF7_USART2) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 4, FMC_NOE, GPIO_AF12_FMC) -#endif -#ifdef OCTOSPI1 -STM32_PIN_FUN_CFG(D, 4, OCTOSPI1_IO4, GPIO_AF10_OCTOSPI1) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 4, USART2_DE, GPIO_AF7_USART2) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 4, USART2_RTS, GPIO_AF7_USART2) -#endif -#ifdef FDCAN1 -STM32_PIN_FUN_CFG(D, 5, FDCAN1_TX, GPIO_AF9_FDCAN1) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 5, FMC_NWE, GPIO_AF12_FMC) -#endif -#ifdef OCTOSPI1 -STM32_PIN_FUN_CFG(D, 5, OCTOSPI1_IO5, GPIO_AF10_OCTOSPI1) -#endif -#ifdef SPI2 -STM32_PIN_FUN_CFG(D, 5, SPI2_RDY, GPIO_AF5_SPI2) -#endif -#ifdef TIM1 -STM32_PIN_FUN_CFG(D, 5, TIM1_CH4N, GPIO_AF1_TIM1) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 5, USART2_TX, GPIO_AF7_USART2) -#endif -#ifdef DCMI -STM32_PIN_FUN_CFG(D, 6, DCMI_D10, GPIO_AF13_DCMI) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 6, FMC_NWAIT, GPIO_AF12_FMC) -#endif -#ifdef I2S3 -STM32_PIN_FUN_CFG(D, 6, I2S3_SDO, GPIO_AF5_SPI3) -#endif -#ifdef OCTOSPI1 -STM32_PIN_FUN_CFG(D, 6, OCTOSPI1_IO6, GPIO_AF10_OCTOSPI1) -#endif -#ifdef PSSI -STM32_PIN_FUN_CFG(D, 6, PSSI_D10, GPIO_AF13_PSSI) -#endif -#ifdef SAI1 -STM32_PIN_FUN_CFG(D, 6, SAI1_D1, GPIO_AF2_SAI1) -#endif -#ifdef SAI1 -STM32_PIN_FUN_CFG(D, 6, SAI1_SD_A, GPIO_AF6_SAI1) -#endif -#ifdef SDMMC2 -STM32_PIN_FUN_CFG(D, 6, SDMMC2_CK, GPIO_AF11_SDMMC2) -#endif -#ifdef SPI3 -STM32_PIN_FUN_CFG(D, 6, SPI3_MOSI, GPIO_AF5_SPI3) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 6, USART2_RX, GPIO_AF7_USART2) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 7, FMC_NCE, GPIO_AF12_FMC) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 7, FMC_NE1, GPIO_AF12_FMC) -#endif -#ifdef I2S1 -STM32_PIN_FUN_CFG(D, 7, I2S1_SDO, GPIO_AF5_SPI1) -#endif -#ifdef LPTIM4 -STM32_PIN_FUN_CFG(D, 7, LPTIM4_OUT, GPIO_AF14_LPTIM4) -#endif -#ifdef OCTOSPI1 -STM32_PIN_FUN_CFG(D, 7, OCTOSPI1_IO7, GPIO_AF10_OCTOSPI1) -#endif -#ifdef SDMMC2 -STM32_PIN_FUN_CFG(D, 7, SDMMC2_CMD, GPIO_AF11_SDMMC2) -#endif -#ifdef SPI1 -STM32_PIN_FUN_CFG(D, 7, SPI1_MOSI, GPIO_AF5_SPI1) -#endif -#ifdef USART2 -STM32_PIN_FUN_CFG(D, 7, USART2_CK, GPIO_AF7_USART2) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 8, FMC_D13, GPIO_AF12_FMC) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 8, FMC_DA13, GPIO_AF12_FMC) -#endif -#ifdef USART3 -STM32_PIN_FUN_CFG(D, 8, USART3_TX, GPIO_AF7_USART3) -#endif -#ifdef FDCAN2 -STM32_PIN_FUN_CFG(D, 9, FDCAN2_RX, GPIO_AF9_FDCAN2) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 9, FMC_D14, GPIO_AF12_FMC) -#endif -#ifdef FMC -STM32_PIN_FUN_CFG(D, 9, FMC_DA14, GPIO_AF12_FMC) -#endif -#ifdef USART3 -STM32_PIN_FUN_CFG(D, 9, USART3_RX, GPIO_AF7_USART3) #endif #endif /* GPIOD */ @@ -2882,7 +2884,7 @@ STM32_PIN_FUN_CFG(G, 9, USART6_RX, GPIO_AF7_USART6) #endif /* GPIOG */ /* Port H definitions */ -#ifdef GPIOH +#if defined(GPIOH) && !defined(STM32H5) #ifdef DCMI STM32_PIN_FUN_CFG(H, 10, DCMI_D1, GPIO_AF13_DCMI) #endif diff --git a/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c b/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c index 6be1a0b62..91de6d08e 100644 --- a/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c +++ b/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c @@ -44,8 +44,10 @@ tinyusb_hardware_init(void) RCC->CCIPR4 = RCC->CCIPR4 | RCC_USBCLKSOURCE_HSI48; } else if (MYNEWT_VAL_CHOICE(USB_CLOCK_SOURCE, pll1_q_ck)) { RCC->CCIPR4 = (RCC->CCIPR4 & ~RCC_CCIPR4_USBSEL) | RCC_USBCLKSOURCE_PLL1Q; +#ifdef RCC_CR_PLL3ON } else if (MYNEWT_VAL_CHOICE(USB_CLOCK_SOURCE, pll3_q_ck)) { RCC->CCIPR4 = (RCC->CCIPR4 & ~RCC_CCIPR4_USBSEL) | RCC_USBCLKSOURCE_PLL3Q; +#endif } /*
