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kasjer pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new 4b8cd6659 bus/spi_stm32: Update driver for H5 and H7
4b8cd6659 is described below
commit 4b8cd66593f1a6b5a718c2efbf98f3db39868f0e
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Fri Sep 25 11:14:05 2026 +0200
bus/spi_stm32: Update driver for H5 and H7
In STM32H5 and STM32H7 SPI peripheral by default
does not stop clock even where FIFO is full.
This results in overrun errors when software does
not read data from FIFO fast enough.
Hardware do have option to stop clock in master
mode when FIFO is full.
Now this functionality is enabled by default
for STM32H5 and STM32H7 devices.
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/bus/drivers/spi_stm32/src/spi_stm32.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/bus/drivers/spi_stm32/src/spi_stm32.c
b/hw/bus/drivers/spi_stm32/src/spi_stm32.c
index ec2305ce5..1964fdfef 100644
--- a/hw/bus/drivers/spi_stm32/src/spi_stm32.c
+++ b/hw/bus/drivers/spi_stm32/src/spi_stm32.c
@@ -952,6 +952,9 @@ bus_spi_stm32_dev_init_func(struct os_dev *odev, void *arg)
dd->hspi.Init.NSS = SPI_NSS_SOFT;
dd->hspi.Init.TIMode = SPI_TIMODE_DISABLE;
dd->hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#if SPI_MASTER_RX_AUTOSUSP_ENABLE
+ dd->hspi.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_ENABLE;
+#endif
#ifdef SPI_MASTER_KEEP_IO_STATE_ENABLE
dd->hspi.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
#endif
