http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h b/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h deleted file mode 100644 index 187bbb1..0000000 --- a/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h +++ /dev/null @@ -1,472 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -/* TIMER */ -#define TIMER0_ENABLED 1 - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 0 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 0 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 1 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 1 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 1 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 0 -/* NOTE: SCK definitions match NRF51 DK product brief */ -#define SPI0_CONFIG_SCK_PIN 29 -#define SPI0_CONFIG_MOSI_PIN 25 -#define SPI0_CONFIG_MISO_PIN 28 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 0 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 0 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 2 -#define SPIS0_CONFIG_MOSI_PIN 3 -#define SPIS0_CONFIG_MISO_PIN 4 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 1 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_SCK_PIN 29 -#define SPIS1_CONFIG_MOSI_PIN 25 -#define SPIS1_CONFIG_MISO_PIN 28 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 -#define UART0_CONFIG_PSEL_TXD 0 -#define UART0_CONFIG_PSEL_RXD 0 -#define UART0_CONFIG_PSEL_CTS 0 -#define UART0_CONFIG_PSEL_RTS 0 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 0 -#define TWI0_CONFIG_SDA 1 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 0 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 0 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 1 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 1 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 0 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 0 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 1 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 1 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 0 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/bsp/nrf51dk-16kbram/include/bsp/nrf_drv_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/nrf51dk-16kbram/include/bsp/nrf_drv_config.h b/hw/bsp/nrf51dk-16kbram/include/bsp/nrf_drv_config.h deleted file mode 100644 index 36c0307..0000000 --- a/hw/bsp/nrf51dk-16kbram/include/bsp/nrf_drv_config.h +++ /dev/null @@ -1,474 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -/* TIMER */ -#define TIMER0_ENABLED 1 - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 0 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 0 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 1 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 1 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 1 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 0 -/* NOTE: SCK definitions match NRF51 DK product brief */ -#define SPI0_CONFIG_CSN_PIN 24 /* Note: not defined by SDK */ -#define SPI0_CONFIG_SCK_PIN 29 -#define SPI0_CONFIG_MOSI_PIN 25 -#define SPI0_CONFIG_MISO_PIN 28 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 0 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 0 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 2 -#define SPIS0_CONFIG_MOSI_PIN 3 -#define SPIS0_CONFIG_MISO_PIN 4 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 1 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_CSN_PIN 24 /* Note: not defined by SDK */ -#define SPIS1_CONFIG_SCK_PIN 29 -#define SPIS1_CONFIG_MOSI_PIN 25 -#define SPIS1_CONFIG_MISO_PIN 28 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 -#define UART0_CONFIG_PSEL_TXD 0 -#define UART0_CONFIG_PSEL_RXD 0 -#define UART0_CONFIG_PSEL_CTS 0 -#define UART0_CONFIG_PSEL_RTS 0 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 7 -#define TWI0_CONFIG_SDA 30 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 0 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 0 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 1 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 1 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 0 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 0 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 1 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 1 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 0 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CONFIG_H http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/bsp/nrf51dk/include/bsp/nrf_drv_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/nrf51dk/include/bsp/nrf_drv_config.h b/hw/bsp/nrf51dk/include/bsp/nrf_drv_config.h deleted file mode 100644 index bd7f62a..0000000 --- a/hw/bsp/nrf51dk/include/bsp/nrf_drv_config.h +++ /dev/null @@ -1,472 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -/* TIMER */ -#define TIMER0_ENABLED 1 - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 0 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 0 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 1 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 1 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 1 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 0 -/* NOTE: SCK definitions match NRF51 DK product brief */ -#define SPI0_CONFIG_SCK_PIN 29 -#define SPI0_CONFIG_MOSI_PIN 25 -#define SPI0_CONFIG_MISO_PIN 28 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 0 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 0 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 2 -#define SPIS0_CONFIG_MOSI_PIN 3 -#define SPIS0_CONFIG_MISO_PIN 4 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 1 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_SCK_PIN 29 -#define SPIS1_CONFIG_MOSI_PIN 25 -#define SPIS1_CONFIG_MISO_PIN 28 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 -#define UART0_CONFIG_PSEL_TXD 0 -#define UART0_CONFIG_PSEL_RXD 0 -#define UART0_CONFIG_PSEL_CTS 0 -#define UART0_CONFIG_PSEL_RTS 0 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 7 -#define TWI0_CONFIG_SDA 30 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 0 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 0 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 1 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 1 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 0 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 0 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 1 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 1 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 0 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CONFIG_H http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/bsp/nrf52dk/include/bsp/nrf_drv_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/nrf52dk/include/bsp/nrf_drv_config.h b/hw/bsp/nrf52dk/include/bsp/nrf_drv_config.h deleted file mode 100644 index 6458bc2..0000000 --- a/hw/bsp/nrf52dk/include/bsp/nrf_drv_config.h +++ /dev/null @@ -1,471 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -/* TIMER */ -#define TIMER0_ENABLED 1 - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 0 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 0 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 1 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 1 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 1 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 1 -#define SPI0_CONFIG_SCK_PIN 23 -#define SPI0_CONFIG_MOSI_PIN 24 -#define SPI0_CONFIG_MISO_PIN 25 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 0 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 1 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 23 -#define SPIS0_CONFIG_MOSI_PIN 24 -#define SPIS0_CONFIG_MISO_PIN 25 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 0 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_SCK_PIN 2 -#define SPIS1_CONFIG_MOSI_PIN 3 -#define SPIS1_CONFIG_MISO_PIN 4 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 -#define UART0_CONFIG_PSEL_TXD 0 -#define UART0_CONFIG_PSEL_RXD 0 -#define UART0_CONFIG_PSEL_CTS 0 -#define UART0_CONFIG_PSEL_RTS 0 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 27 -#define TWI0_CONFIG_SDA 26 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 1 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 1 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 1 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 0 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 1 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 1 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 1 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 1 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 1 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CONFIG_H http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h b/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h deleted file mode 100644 index b5c7806..0000000 --- a/hw/bsp/rb-nano2/include/bsp/nrf_drv_config.h +++ /dev/null @@ -1,471 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 -#endif - -/* TIMER */ -#define TIMER0_ENABLED 1 - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 0 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 0 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 1 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 1 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 1 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 1 -#define SPI0_CONFIG_SCK_PIN 2 -#define SPI0_CONFIG_MOSI_PIN 3 -#define SPI0_CONFIG_MISO_PIN 4 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 0 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 1 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 23 -#define SPIS0_CONFIG_MOSI_PIN 24 -#define SPIS0_CONFIG_MISO_PIN 25 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 0 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_SCK_PIN 2 -#define SPIS1_CONFIG_MOSI_PIN 3 -#define SPIS1_CONFIG_MISO_PIN 4 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200 -#define UART0_CONFIG_PSEL_TXD 0 -#define UART0_CONFIG_PSEL_RXD 0 -#define UART0_CONFIG_PSEL_CTS 0 -#define UART0_CONFIG_PSEL_RTS 0 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 0 -#define TWI0_CONFIG_SDA 1 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 1 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 1 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 1 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 0 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 1 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 1 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 1 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 1 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 1 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#ifdef __cplusplus -} -#endif - -#endif // NRF_DRV_CONFIG_H http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/mcu/nordic/nrf51xxx/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/mcu/nordic/nrf51xxx/pkg.yml b/hw/mcu/nordic/nrf51xxx/pkg.yml index fad358c..1043c16 100644 --- a/hw/mcu/nordic/nrf51xxx/pkg.yml +++ b/hw/mcu/nordic/nrf51xxx/pkg.yml @@ -25,7 +25,7 @@ pkg.keywords: - nrf51 pkg.deps: - - hw/hal - - hw/cmsis-core - - hw/mcu/nordic + - '@mynewt_nordic/hw/mcu/nordic_sdk' - compiler/arm-none-eabi-m0 + - hw/cmsis-core + - hw/hal http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/mcu/nordic/nrf52xxx/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/mcu/nordic/nrf52xxx/pkg.yml b/hw/mcu/nordic/nrf52xxx/pkg.yml index ae087c0..a9d4862 100644 --- a/hw/mcu/nordic/nrf52xxx/pkg.yml +++ b/hw/mcu/nordic/nrf52xxx/pkg.yml @@ -25,7 +25,7 @@ pkg.keywords: - nrf52 pkg.deps: - - hw/hal - - hw/mcu/nordic - - hw/cmsis-core + - '@mynewt_nordic/hw/mcu/nordic_sdk' - compiler/arm-none-eabi-m4 + - hw/cmsis-core + - hw/hal http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a1481cb2/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/adc/nrf_drv_adc.c ---------------------------------------------------------------------- diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/adc/nrf_drv_adc.c b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/adc/nrf_drv_adc.c deleted file mode 100644 index 5a81002..0000000 --- a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/drivers_nrf/adc/nrf_drv_adc.c +++ /dev/null @@ -1,253 +0,0 @@ -/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#include "nrf_drv_adc.h" -#include "nrf_drv_common.h" -#include "nrf_assert.h" -#include "app_util_platform.h" -#include "app_util.h" - -typedef struct -{ - nrf_drv_adc_event_handler_t event_handler; - nrf_drv_adc_channel_t * p_head; - nrf_drv_adc_channel_t * p_current_conv; - nrf_adc_value_t * p_buffer; - uint8_t size; - uint8_t idx; - nrf_drv_state_t state; -} adc_cb_t; - -static adc_cb_t m_cb; -static const nrf_drv_adc_config_t m_default_config = NRF_DRV_ADC_DEFAULT_CONFIG; - -ret_code_t nrf_drv_adc_init(nrf_drv_adc_config_t const * p_config, - nrf_drv_adc_event_handler_t event_handler) -{ - if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) - { - return NRF_ERROR_INVALID_STATE; - } - - nrf_adc_event_clear(NRF_ADC_EVENT_END); - if (event_handler) - { - if (!p_config) - { - p_config = (nrf_drv_adc_config_t *)&m_default_config; - } - nrf_drv_common_irq_enable(ADC_IRQn, p_config->interrupt_priority); - } - m_cb.event_handler = event_handler; - m_cb.state = NRF_DRV_STATE_INITIALIZED; - - return NRF_SUCCESS; -} - -void nrf_drv_adc_uninit(void) -{ - m_cb.p_head = NULL; - nrf_drv_common_irq_disable(ADC_IRQn); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_task_trigger(NRF_ADC_TASK_STOP); - - m_cb.state = NRF_DRV_STATE_UNINITIALIZED; -} - -void nrf_drv_adc_channel_enable(nrf_drv_adc_channel_t * const p_channel) -{ - ASSERT(mp_state == NRF_DRV_STATE_INITIALIZED); - ASSERT(!is_address_from_stack(p_channel)); - - p_channel->p_next = NULL; - if (m_cb.p_head == NULL) - { - m_cb.p_head = p_channel; - } - else - { - nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head; - while (p_curr_channel->p_next != NULL) - { - ASSERT(p_channel != p_curr_channel); - p_curr_channel = p_curr_channel->p_next; - } - p_curr_channel->p_next = p_channel; - } -} - -void nrf_drv_adc_channel_disable(nrf_drv_adc_channel_t * const p_channel) -{ - ASSERT(mp_state == NRF_DRV_STATE_INITIALIZED); - ASSERT(m_cb.p_head); - - nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head; - nrf_drv_adc_channel_t * p_prev_channel = NULL; - while(p_curr_channel != p_channel) - { - p_prev_channel = p_curr_channel; - p_curr_channel = p_curr_channel->p_next; - ASSERT(p_curr_channel == NULL); - } - if (p_prev_channel) - { - p_prev_channel->p_next = p_curr_channel->p_next; - } - else - { - m_cb.p_head = p_curr_channel->p_next; - } -} - -void nrf_drv_adc_sample(void) -{ - ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED); - ASSERT(!nrf_adc_is_busy()); - nrf_adc_start(); -} - -ret_code_t nrf_drv_adc_sample_convert(nrf_drv_adc_channel_t const * const p_channel, - nrf_adc_value_t * p_value) -{ - ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED); - if(m_cb.state == NRF_DRV_STATE_POWERED_ON) - { - return NRF_ERROR_BUSY; - } - else - { - m_cb.state = NRF_DRV_STATE_POWERED_ON; - - nrf_adc_config_set(p_channel->config.data); - nrf_adc_enable(); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_start(); - if (p_value) - { - while(!nrf_adc_event_check(NRF_ADC_EVENT_END)) {} - nrf_adc_event_clear(NRF_ADC_EVENT_END); - *p_value = (nrf_adc_value_t)nrf_adc_result_get(); - nrf_adc_disable(); - - m_cb.state = NRF_DRV_STATE_INITIALIZED; - } - else - { - ASSERT(m_cb.event_handler); - m_cb.p_buffer = NULL; - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - return NRF_SUCCESS; - } -} - -static bool adc_sample_process() -{ - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_disable(); - m_cb.p_buffer[m_cb.idx] = (nrf_adc_value_t)nrf_adc_result_get(); - m_cb.idx++; - if (m_cb.idx < m_cb.size) - { - bool task_trigger = false; - if (m_cb.p_current_conv->p_next == NULL) - { - m_cb.p_current_conv = m_cb.p_head; - } - else - { - m_cb.p_current_conv = m_cb.p_current_conv->p_next; - task_trigger = true; - } - nrf_adc_config_set(m_cb.p_current_conv->config.data); - nrf_adc_enable(); - if (task_trigger) - { - //nrf_adc_start(); - nrf_adc_task_trigger(NRF_ADC_TASK_START); - } - return false; - } - else - { - return true; - } -} - -ret_code_t nrf_drv_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size) -{ - ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED); - if(m_cb.state == NRF_DRV_STATE_POWERED_ON) - { - return NRF_ERROR_BUSY; - } - else - { - m_cb.state = NRF_DRV_STATE_POWERED_ON; - m_cb.p_current_conv = m_cb.p_head; - m_cb.size = size; - m_cb.idx = 0; - m_cb.p_buffer = buffer; - nrf_adc_config_set(m_cb.p_current_conv->config.data); - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_enable(); - if (m_cb.event_handler) - { - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - else - { - while(1) - { - while(!nrf_adc_event_check(NRF_ADC_EVENT_END)){} - - if (adc_sample_process()) - { - m_cb.state = NRF_DRV_STATE_INITIALIZED; - break; - } - } - } - return NRF_SUCCESS; - } -} - -bool nrf_drv_adc_is_busy(void) -{ - ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED); - return (m_cb.state == NRF_DRV_STATE_POWERED_ON) ? true : false; -} - -void ADC_IRQHandler(void) -{ - if (m_cb.p_buffer == NULL) - { - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_disable(); - nrf_drv_adc_evt_t evt; - evt.type = NRF_DRV_ADC_EVT_SAMPLE; - evt.data.sample.sample = (nrf_adc_value_t)nrf_adc_result_get(); - m_cb.state = NRF_DRV_STATE_INITIALIZED; - m_cb.event_handler(&evt); - } - else if (adc_sample_process()) - { - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_drv_adc_evt_t evt; - evt.type = NRF_DRV_ADC_EVT_DONE; - evt.data.done.p_buffer = m_cb.p_buffer; - evt.data.done.size = m_cb.size; - m_cb.state = NRF_DRV_STATE_INITIALIZED; - m_cb.event_handler(&evt); - } -}
