francois-berder commented on a change in pull request #329: Wi-Fire: Implement hal_timer URL: https://github.com/apache/incubator-mynewt-core/pull/329#discussion_r121670619
########## File path: hw/mcu/microchip/pic32mz2048efg100/src/hal_timer.c ########## @@ -0,0 +1,548 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <os/os.h> +#include <stdint.h> +#include <xc.h> +#include "hal/hal_timer.h" +#include "mcu/mips_hal.h" + +#define PIC32MZ_TIMER_COUNT (8) +#define PIC32MZ_PRESCALER_COUNT (8) + +#define TxCON(T) (base_address[T][0x0 / 0x4]) +#define TxCONCLR(T) (base_address[T][0x4 / 0x4]) +#define TxCONSET(T) (base_address[T][0x8 / 0x4]) +#define TMRx(T) (base_address[T][0x10 / 0x4]) +#define PRx(T) (base_address[T][0x20 / 0x4]) + +static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = { + (volatile uint32_t *)_TMR2_BASE_ADDRESS, + (volatile uint32_t *)_TMR3_BASE_ADDRESS, + (volatile uint32_t *)_TMR4_BASE_ADDRESS, + (volatile uint32_t *)_TMR5_BASE_ADDRESS, + (volatile uint32_t *)_TMR6_BASE_ADDRESS, + (volatile uint32_t *)_TMR7_BASE_ADDRESS, + (volatile uint32_t *)_TMR8_BASE_ADDRESS, + (volatile uint32_t *)_TMR9_BASE_ADDRESS +}; + +static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] = +{1, 2, 4, 8, 16, 32, 64, 256}; +struct pic32_timer { + uint32_t index; + uint64_t interrupt_count; + uint32_t interrupt_per_tick; + uint64_t expiry; /* The unit is number of interrupts */ + TAILQ_HEAD(hal_timer_qhead, hal_timer) hal_timer_queue; +}; +static struct pic32_timer timers[PIC32MZ_TIMER_COUNT]; + + +static inline uint32_t +hal_timer_get_prescaler(int timer_num) +{ + uint32_t index = + (TxCON(timer_num) & _T2CON_TCKPS_MASK) >> _T2CON_TCKPS_POSITION; + return timer_prescalers[index]; +} + +static inline uint32_t +hal_timer_get_peripheral_base_clock(void) +{ + return MYNEWT_VAL(CLOCK_FREQ) / ((PB3DIV & _PB3DIV_PBDIV_MASK) + 1); +} + +static void +hal_timer_enable_int(int timer_num) +{ + switch (timer_num) { + case 0: + IPC2CLR = _IPC2_T2IP_MASK | _IPC2_T2IS_MASK; + IPC2SET = 3 << _IPC2_T2IP_POSITION; + IFS0CLR = _IFS0_T2IF_MASK; + IEC0SET = _IEC0_T2IE_MASK; + break; + case 1: + IPC3CLR = _IPC3_T3IP_MASK | _IPC3_T3IS_MASK; + IPC3SET = 3 << _IPC3_T3IP_POSITION; + IFS0CLR = _IFS0_T3IF_MASK; + IEC0SET = _IEC0_T3IE_MASK; + break; + case 2: + IPC4CLR = _IPC4_T4IP_MASK | _IPC4_T4IS_MASK; + IPC4SET = 3 << _IPC4_T4IP_POSITION; + IFS0CLR = _IFS0_T4IF_MASK; + IEC0SET = _IEC0_T4IE_MASK; + break; + case 3: + IPC6CLR = _IPC6_T5IP_MASK | _IPC6_T5IS_MASK; + IPC6SET = 3 << _IPC6_T5IP_POSITION; + IFS0CLR = _IFS0_T5IF_MASK; + IEC0SET = _IEC0_T5IE_MASK; + break; + case 4: + IPC7CLR = _IPC7_T6IP_MASK | _IPC7_T6IS_MASK; + IPC7SET = 3 << _IPC7_T6IP_POSITION; + IFS0CLR = _IFS0_T6IF_MASK; + IEC0SET = _IEC0_T6IE_MASK; + break; + case 5: + IPC8CLR = _IPC8_T7IP_MASK | _IPC8_T7IS_MASK; + IPC8SET = 3 << _IPC8_T7IP_POSITION; + IFS1CLR = _IFS1_T7IF_MASK; + IEC1SET = _IEC1_T7IE_MASK; + break; + case 6: + IPC9CLR = _IPC9_T8IP_MASK | _IPC9_T8IS_MASK; + IPC9SET = 3 << _IPC9_T8IP_POSITION; + IFS1CLR = _IFS1_T8IF_MASK; + IEC1SET = _IEC1_T8IE_MASK; + break; + case 7: + IPC10CLR = _IPC10_T9IP_MASK | _IPC10_T9IS_MASK; + IPC10SET = 3 << _IPC10_T9IP_POSITION; + IFS1CLR = _IFS1_T9IF_MASK; + IEC1SET = _IEC1_T9IE_MASK; + break; + } +} + +static void +hal_timer_disable_int(int timer_num) +{ + switch (timer_num) { + case 0: + IEC0CLR = _IEC0_T2IE_MASK; + IFS0CLR = _IFS0_T2IF_MASK; + break; + case 1: + IEC0CLR = _IEC0_T3IE_MASK; + IFS0CLR = _IFS0_T3IF_MASK; + break; + case 2: + IEC0CLR = _IEC0_T4IE_MASK; + IFS0CLR = _IFS0_T4IF_MASK; + break; + case 3: + IEC0CLR = _IEC0_T5IE_MASK; + IFS0CLR = _IFS0_T5IF_MASK; + break; + case 4: + IEC0CLR = _IEC0_T6IE_MASK; + IFS0CLR = _IFS0_T6IF_MASK; + break; + case 5: + IEC1CLR = _IEC1_T7IE_MASK; + IFS1CLR = _IFS1_T7IF_MASK; + break; + case 6: + IEC1CLR = _IEC1_T8IE_MASK; + IFS1CLR = _IFS1_T8IF_MASK; + break; + case 7: + IEC1CLR = _IEC1_T9IE_MASK; + IFS1CLR = _IFS1_T9IF_MASK; + break; + } + +} + +static void +compute_next_expiry(struct pic32_timer *bsp_timer) +{ + struct hal_timer *first = TAILQ_FIRST(&bsp_timer->hal_timer_queue); + if (first != NULL) { + bsp_timer->expiry = first->expiry; + bsp_timer->expiry *= bsp_timer->interrupt_per_tick; + } +} + +static void +handle_timer_list(int timer_num) +{ + int i; + int timers_to_remove = 0; + uint32_t current_tick = hal_timer_read(timer_num); + struct hal_timer *entry; + + TAILQ_FOREACH(entry, &timers[timer_num].hal_timer_queue, link) { + if (entry->expiry <= current_tick) { + entry->cb_func(entry->cb_arg); + ++timers_to_remove; + } else { + break; + } + } + + for (i = 0; i < timers_to_remove; ++i) { + TAILQ_REMOVE(&timers[timer_num].hal_timer_queue, + TAILQ_FIRST(&timers[timer_num].hal_timer_queue), link); + } + if (timers_to_remove != 0) { + compute_next_expiry(&timers[timer_num]); + } +} + +void +__attribute__((interrupt(IPL3AUTO), vector(_TIMER_2_VECTOR))) +timer2_isr(void) +{ + ++timers[0].interrupt_count; + + if (!(TAILQ_EMPTY(&timers[0].hal_timer_queue)) && + timers[0].expiry <= timers[0].interrupt_count) { Review comment: I tested my code by setting a timer at 500kHz and I was already hitting some issues because the ```hal_timer_read``` took too much time to execute in the interrupt handler, that is why I used interrupt count to make ```hal_timer_read``` as fast as possible. > Is there a register you can read for the time instead of relying on interrupt count? Yes I can use ```PRx``` and ```TMRx```. I was looking at the nrf51xxx hal_timer implementation and I found out two things: - The tick does not seem to be related to ```OS_TICKS_PER_SEC```. Having a 64-bit counter that increases at a fixed rate would be the current tick of the timer. - The ```hal_config``` only seems to configure prescaler as the compare register is changed when a soft timer is added/removed in the list to generate as few interrupts as possible. From my understanding, the parameter ```freq_hz``` in ```hal_config``` does not specify the frequency of interrupts generated by the timer module, but instead specifies the speed of increase of the ```TMRx``` register. Are these two assumptions correct ? ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on GitHub and use the URL above to go to the specific comment. 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