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new 38b043d arch/arm/src/stm32f7/: Apply fix introduced by 0947b31fbbd
for STM32F7[6/7]XX to STM32F7[2/3/4/5]XX.
38b043d is described below
commit 38b043da9fdfa9e00810308c5bfd2aa27220757c
Author: Björn Brandt <[email protected]>
AuthorDate: Wed Jan 8 07:09:49 2020 -0600
arch/arm/src/stm32f7/: Apply fix introduced by 0947b31fbbd for
STM32F7[6/7]XX to STM32F7[2/3/4/5]XX.
In RCC configuration, STM32_RCC_DCKCFGR2 has nothing to do with PLLI2S;
PLLI2S is not dependent on LTDC, instead on SAICLK1/2 generated from PLLI2S
---
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 32 ++++++++++++++++---------------
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 32 ++++++++++++++++---------------
2 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
index c648853..bdead95 100644
--- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
@@ -866,7 +866,7 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
- /* Configure PLLSAI */
+ /* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
@@ -918,8 +918,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
-#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
+#if defined(CONFIG_STM32F7_PLLI2S) || \
+ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
+ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
@@ -937,6 +939,19 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
+ /* Enable PLLI2S */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= RCC_CR_PLLI2SON;
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Wait until the PLLI2S is ready */
+
+ while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
+ {
+ }
+#endif
+
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
@@ -978,19 +993,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR2);
- /* Enable PLLI2S */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_PLLI2SON;
- putreg32(regval, STM32_RCC_CR);
-
- /* Wait until the PLLI2S is ready */
-
- while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
- {
- }
-#endif
-
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
index 4f571e9..693b742 100644
--- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
@@ -863,7 +863,7 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
- /* Configure PLLSAI */
+ /* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
@@ -905,8 +905,10 @@ static void stm32_stdclockconfig(void)
{
}
#endif
-#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
+#if defined(CONFIG_STM32F7_PLLI2S) || \
+ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \
+ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
@@ -920,6 +922,19 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
putreg32(regval, STM32_RCC_PLLI2SCFGR);
+ /* Enable PLLI2S */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= RCC_CR_PLLI2SON;
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Wait until the PLLI2S is ready */
+
+ while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
+ {
+ }
+#endif
+
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
| RCC_DCKCFGR2_USART2SEL_MASK
@@ -955,19 +970,6 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_DCKCFGR2);
- /* Enable PLLI2S */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_PLLI2SON;
- putreg32(regval, STM32_RCC_CR);
-
- /* Wait until the PLLI2S is ready */
-
- while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
- {
- }
-#endif
-
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
