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commit 856c3e4263d46e404b5de387ba3c738d9d73f81a Author: Matias Nitsche <[email protected]> AuthorDate: Mon May 11 18:51:21 2020 -0300 nxstyle fixes --- boards/arm/stm32/common/include/stm32_apds9960.h | 2 +- boards/arm/stm32/common/include/stm32_zerocross.h | 2 +- boards/arm/stm32/common/src/stm32_apds9960.c | 6 +-- boards/arm/stm32/common/src/stm32_hcsr04.c | 16 ++++--- boards/arm/stm32/stm32f4discovery/include/board.h | 52 +++++++++++++---------- 5 files changed, 43 insertions(+), 35 deletions(-) diff --git a/boards/arm/stm32/common/include/stm32_apds9960.h b/boards/arm/stm32/common/include/stm32_apds9960.h index eed7cf5..d016b81 100644 --- a/boards/arm/stm32/common/include/stm32_apds9960.h +++ b/boards/arm/stm32/common/include/stm32_apds9960.h @@ -1,5 +1,5 @@ /**************************************************************************** - * /home/v01d/coding/nuttx_latest/nuttx/boards/arm/stm32/common/include/stm32_apds9960.h + * boards/arm/stm32/common/include/stm32_apds9960.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/common/include/stm32_zerocross.h b/boards/arm/stm32/common/include/stm32_zerocross.h index 3e2d0c3..d742745 100644 --- a/boards/arm/stm32/common/include/stm32_zerocross.h +++ b/boards/arm/stm32/common/include/stm32_zerocross.h @@ -1,5 +1,5 @@ /**************************************************************************** - * /home/v01d/coding/nuttx_latest/nuttx/boards/arm/stm32/common/include/stm32_zerocross.h + * boards/arm/stm32/common/include/stm32_zerocross.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/common/src/stm32_apds9960.c b/boards/arm/stm32/common/src/stm32_apds9960.c index efd31a7..ce17b33 100644 --- a/boards/arm/stm32/common/src/stm32_apds9960.c +++ b/boards/arm/stm32/common/src/stm32_apds9960.c @@ -94,9 +94,9 @@ static int apds9960_irq_attach(FAR struct apds9960_config_s *state, static struct stm32_apds9960config_s g_apds9960config = { .config = - { - .irq_attach = apds9960_irq_attach, - }, + { + .irq_attach = apds9960_irq_attach, + }, }; /**************************************************************************** diff --git a/boards/arm/stm32/common/src/stm32_hcsr04.c b/boards/arm/stm32/common/src/stm32_hcsr04.c index 0aa54c3..9dee94b 100644 --- a/boards/arm/stm32/common/src/stm32_hcsr04.c +++ b/boards/arm/stm32/common/src/stm32_hcsr04.c @@ -145,8 +145,8 @@ static int hcsr04_irq_attach(FAR struct hcsr04_config_s *state, xcpt_t isr, priv->isr = isr; priv->arg = arg; - stm32_gpiosetevent(BOARD_HCSR04_GPIO_INT, priv->rising, priv->falling, true, - isr, arg); + stm32_gpiosetevent(BOARD_HCSR04_GPIO_INT, priv->rising, priv->falling, + true, isr, arg); leave_critical_section(flags); @@ -155,7 +155,8 @@ static int hcsr04_irq_attach(FAR struct hcsr04_config_s *state, xcpt_t isr, /* Setup the interruption mode: Rising or Falling */ -static void hcsr04_irq_setmode(FAR struct hcsr04_config_s *state, bool rise_mode) +static void hcsr04_irq_setmode(FAR struct hcsr04_config_s *state, + bool rise_mode) { FAR struct stm32_hcsr04config_s *priv = (FAR struct stm32_hcsr04config_s *)state; @@ -182,20 +183,21 @@ static void hcsr04_irq_enable(FAR const struct hcsr04_config_s *state, iinfo("%d\n", enable); - stm32_gpiosetevent(BOARD_HCSR04_GPIO_INT, priv->rising, priv->falling, true, - enable ? priv->isr : NULL, priv->arg); + stm32_gpiosetevent(BOARD_HCSR04_GPIO_INT, priv->rising, priv->falling, + true, enable ? priv->isr : NULL, priv->arg); } /* Acknowledge/clear any pending GPIO interrupt */ static void hcsr04_irq_clear(FAR const struct hcsr04_config_s *state) { - // FIXME Nothing to do ? + /* FIXME: Nothing to do ? */ } /* Set the Trigger pin state */ -static void hcsr04_set_trigger(FAR const struct hcsr04_config_s *state, bool on) +static void hcsr04_set_trigger(FAR const struct hcsr04_config_s *state, + bool on) { stm32_gpiowrite(BOARD_HCSR04_GPIO_TRIG, on); } diff --git a/boards/arm/stm32/stm32f4discovery/include/board.h b/boards/arm/stm32/stm32f4discovery/include/board.h index b4cf157..528f178 100644 --- a/boards/arm/stm32/stm32f4discovery/include/board.h +++ b/boards/arm/stm32/stm32f4discovery/include/board.h @@ -53,14 +53,15 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ -/* The STM32F4 Discovery board features a single 8MHz crystal. Space is provided - * for a 32kHz RTC backup crystal, but it is not stuffed. +/* The STM32F4 Discovery board features a single 8MHz crystal. + * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. * * This is the canonical configuration: * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) @@ -70,7 +71,8 @@ * PLLN : 336 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK * Flash Latency(WS) : 5 * Prefetch Buffer : OFF * Instruction cache : ON @@ -192,10 +194,10 @@ # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -218,8 +220,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * stm32f4discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f4discovery. The following definitions describe how NuttX + * controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -231,7 +234,7 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ /* The STM32F4 Discovery supports one button: */ @@ -239,7 +242,7 @@ #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* CAN */ @@ -259,7 +262,8 @@ * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial * device. (See the README.txt file for other options) * - * These pins selections, however, conflict with pin usage on the STM32F4DIS-BB. + * These pins selections, however, conflict with pin usage on the + * STM32F4DIS-BB. */ #ifndef CONFIG_STM32F4DISBB @@ -293,9 +297,11 @@ /* USART6: * * The STM32F4DIS-BB base board provides RS-232 drivers and a DB9 connector - * for USART6. This is the preferred serial console for use with the STM32F4DIS-BB. + * for USART6. This is the preferred serial console for use with the + * STM32F4DIS-BB. * - * NOTE: CTS and RTS are not brought out to the RS-232 connector on the baseboard. + * NOTE: CTS and RTS are not brought out to the RS-232 connector on the + * baseboard. */ #define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 (also I2S3_MCK and P2 pin 48) */ @@ -303,8 +309,8 @@ /* PWM * - * The STM32F4 Discovery has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM4 CH2 on PD13. + * The STM32F4 Discovery has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM4 CH2 on PD13. */ #define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 @@ -358,8 +364,8 @@ #define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 #define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 -/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and I2C1_SDA are - * available on the following pins: +/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and + * I2C1_SDA are available on the following pins: * * - PB6 is I2C1_SCL * - PB9 is I2C1_SDA @@ -376,7 +382,7 @@ #define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1 #define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1 -/* Ethernet *************************************************************************/ +/* Ethernet *****************************************************************/ #if defined(CONFIG_STM32F4DISBB) && defined(CONFIG_STM32_ETHMAC) /* RMII interface to the LAN8720 PHY */ @@ -408,10 +414,10 @@ GPIO_PORTC | GPIO_PIN1) #endif -/* DMA Channel/Stream Selections ****************************************************/ +/* DMA Channel/Stream Selections ********************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3
