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commit 62342243255f714dab4ba6675388e5449ad815f8 Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Fri Dec 15 13:31:04 2023 -0300 esp32s2: Integrate Espressif HAL repository to ESP32-S2 By integrating the Espressif`s HAL repository into the current ESP32-S2 implementation on NuttX, it is possible to call functions that makes it easier to setup the registers of the ESP32-S2, enabling the usage of common Espressif drivers. --- arch/xtensa/src/esp32s2/Kconfig | 6 ++ arch/xtensa/src/esp32s2/Make.defs | 10 ++- arch/xtensa/src/esp32s2/esp32s2_clockconfig.c | 39 --------- arch/xtensa/src/esp32s2/esp32s2_clockconfig.h | 34 +------- arch/xtensa/src/esp32s2/esp32s2_gpio.c | 3 + arch/xtensa/src/esp32s2/esp32s2_gpio.h | 38 ++++++--- arch/xtensa/src/esp32s2/esp32s2_rtc.c | 3 - arch/xtensa/src/esp32s2/hal.mk | 97 ++++++++++++++++++++++ .../esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c | 2 +- .../esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c | 2 +- .../esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c | 2 +- .../esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c | 2 +- 12 files changed, 149 insertions(+), 89 deletions(-) diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index 0cf493e409..2f37780fda 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -21,6 +21,10 @@ config ARCH_CHIP_ESP32S2WROVER endchoice # ESP32-S2 Chip Selection +config ESPRESSIF_CHIP_SERIES + string + default "esp32s2" + choice ESP32S2_DEFAULT_CPU_FREQ prompt "CPU Frequency" default ESP32S2_DEFAULT_CPU_FREQ_240 @@ -191,6 +195,8 @@ config ESP32S2_RUN_IRAM menu "ESP32-S2 Peripheral Selection" +source "arch/xtensa/src/common/espressif/Kconfig" + config ESP32S2_UART bool default n diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs index 4621feaefb..fca3569fe7 100644 --- a/arch/xtensa/src/esp32s2/Make.defs +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -151,7 +151,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 2fbc8a025275d68833cdfef490377048538de57a + ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd endif ifndef ESP_HAL_3RDPARTY_URL @@ -168,7 +168,15 @@ chip/$(ESP_HAL_3RDPARTY_REPO): CFLAGS += -Wno-undef -Wno-unused-variable +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +include chip/hal.mk + +include common/espressif/Make.defs + include chip/Bootloader.mk +context:: chip/$(ESP_HAL_3RDPARTY_REPO) + distclean:: $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c index d722fec970..610a789c27 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c @@ -281,42 +281,3 @@ void esp32s2_clockconfig(void) esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); } - -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get CPU frequency - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_cpu_freq(void) -{ - return g_ticks_per_us * MHZ; -} - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * APB clock frequency, in Hz - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_apb_freq(void) -{ - return MIN(g_ticks_per_us, 80) * MHZ; -} - diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h index a0f05b109b..3e9b8d4637 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h @@ -27,6 +27,8 @@ #include <nuttx/config.h> +#include "esp_private/esp_clk.h" + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -77,36 +79,4 @@ void esp32s2_set_cpu_freq(int cpu_freq_mhz); void esp32s2_clockconfig(void); -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get CPU frequency - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int esp_clk_cpu_freq(void); - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * APB clock frequency, in Hz - * - ****************************************************************************/ - -int esp_clk_apb_freq(void); - #endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_gpio.c index cfe8baf516..4463899529 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_gpio.c +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.c @@ -34,6 +34,9 @@ #include <nuttx/irq.h> #include "xtensa.h" + +#include "soc/soc_caps.h" + #include "esp32s2_gpio.h" #include "esp32s2_irq.h" #include "hardware/esp32s2_gpio.h" diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/esp32s2_gpio.h index 7e3d2aff4b..0e68f75eae 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_gpio.h +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.h @@ -93,6 +93,33 @@ # define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) # define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) +/* Interrupt type used with esp32s2_gpioirqenable() */ + +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 + +/* Check whether it is a valid GPIO number */ + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & \ + SOC_GPIO_VALID_GPIO_MASK) != 0)) + +/* Check whether it can be a valid GPIO number of output mode */ + +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) + +/* Check whether it can be a valid digital I/O pad */ + +#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -102,16 +129,7 @@ /* Must be big enough to hold the above encodings */ typedef uint16_t gpio_pinattr_t; - -typedef enum gpio_intrtype_e -{ - GPIO_INTR_DISABLE = 0, /* Disable GPIO interrupt */ - GPIO_INTR_POSEDGE = 1, /* Rising edge */ - GPIO_INTR_NEGEDGE = 2, /* Falling edge */ - GPIO_INTR_ANYEDGE = 3, /* Both rising and falling edge */ - GPIO_INTR_LOW_LEVEL = 4, /* Input low level trigger */ - GPIO_INTR_HIGH_LEVEL = 5 /* Input high level trigger */ -} gpio_intrtype_t; +typedef uint8_t gpio_intrtype_t; /**************************************************************************** * Public Data diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c index 9f61ad1912..b8e777c3ff 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.c @@ -1311,9 +1311,6 @@ uint32_t IRAM_ATTR esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, return period; } -enum esp32s2_rtc_xtal_freq_e rtc_get_xtal(void) - __attribute__((alias("esp32s2_rtc_clk_xtal_freq_get"))); - /**************************************************************************** * Name: esp32s2_rtc_clk_xtal_freq_get * diff --git a/arch/xtensa/src/esp32s2/hal.mk b/arch/xtensa/src/esp32s2/hal.mk new file mode 100644 index 0000000000..cd59abb11d --- /dev/null +++ b/arch/xtensa/src/esp32s2/hal.mk @@ -0,0 +1,97 @@ +############################################################################ +# arch/xtensa/src/esp32s2/hal.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include header paths + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include + +# Linker scripts + +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld + +# Source files + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c + +CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c index bd0b5032d8..a945d9b9ae 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c @@ -328,7 +328,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) /* Configure the interrupt for rising and falling edges */ - esp32s2_gpioirqenable(irq, GPIO_INTR_ANYEDGE); + esp32s2_gpioirqenable(irq, CHANGE); } else { diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c index fd5aebde92..935fa13dd2 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c @@ -374,7 +374,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s2_gpioirqenable(irq, GPIO_INTR_POSEDGE); + esp32s2_gpioirqenable(irq, RISING); } } else diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c index 0b2a1f2e72..c8444482ba 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c @@ -154,7 +154,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) /* Configure the interrupt for rising and falling edges */ - esp32s2_gpioirqenable(irq, GPIO_INTR_ANYEDGE); + esp32s2_gpioirqenable(irq, CHANGE); } else { diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c index 9c66d0b2d4..10e18f703f 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c @@ -374,7 +374,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s2_gpioirqenable(irq, GPIO_INTR_POSEDGE); + esp32s2_gpioirqenable(irq, RISING); } } else
