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The following commit(s) were added to refs/heads/master by this push:
new b7bd2e33b1 arm/armv8-r: wfi secondary cores if SMP is disabled
b7bd2e33b1 is described below
commit b7bd2e33b124d51aa64582a1a7bb4584c511f6c2
Author: chao an <anc...@lixiang.com>
AuthorDate: Thu Jan 11 11:09:50 2024 +0800
arm/armv8-r: wfi secondary cores if SMP is disabled
Check cpu affinity in single core mode to avoid secondary cores bootup
Signed-off-by: chao an <anc...@lixiang.com>
---
arch/arm/src/armv8-r/arm_head.S | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/armv8-r/arm_head.S b/arch/arm/src/armv8-r/arm_head.S
index ed1f059312..1ff6b05aee 100644
--- a/arch/arm/src/armv8-r/arm_head.S
+++ b/arch/arm/src/armv8-r/arm_head.S
@@ -132,12 +132,12 @@
.type __start, #function
__start:
-#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
/* Get cpuindex, cpu0 continue boot, others wait event from cpu0 */
mrc CP15_MPIDR(r0)
and r0, r0, #0x3
cmp r0, #0
+#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
beq __cpu0_start
wfe
cmp r0, #1
@@ -155,9 +155,21 @@ __start:
beq __cpu4_start
# endif
-__cpu0_start:
+#else
+ beq __cpu0_start
+
+__cpux_wfi:
+
+ /* Clear all pending data access */
+
+ dsb sy
+ wfi
+ b __cpux_wfi
+
#endif
+__cpu0_start:
+
/* Make sure that IRQs and FIQs are disabled */
cpsid if
