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commit c352b04155c409cf54f333e1ee452a3bd05cca9d Author: Yanfeng Liu <[email protected]> AuthorDate: Mon May 6 13:54:09 2024 +0800 risc-v/sbi: add SRST extenstion usage in S-mode This adds SBI specfication v0.3 based `riscv_sbi_system_reset()` to support SBI firmware based system reset in kernel mode. Signed-off-by: Yanfeng Liu <[email protected]> --- arch/Kconfig | 1 + arch/risc-v/src/common/riscv_internal.h | 17 +++++++++++++++++ arch/risc-v/src/common/supervisor/riscv_sbi.c | 10 ++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 3efa5849d7..4a116607c8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -92,6 +92,7 @@ config ARCH_RISCV select ARCH_HAVE_RDWR_MEM_CPU_RUN select ARCH_HAVE_TCBINFO select ARCH_HAVE_THREAD_LOCAL + select ARCH_HAVE_POWEROFF select ARCH_HAVE_LAZYFPU if ARCH_HAVE_FPU ---help--- RISC-V 32 and 64-bit RV32 / RV64 architectures. diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index 4365a42e60..c54c8b3fea 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -173,6 +173,7 @@ #define SBI_EXT_HSM 0x48534D #define SBI_EXT_IPI 0x735049 #define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 /* SBI function IDs for TIME extension */ @@ -186,6 +187,21 @@ #define SBI_EXT_IPI_SEND_IPI 0x0 +/* SBI function IDs for SRST extension */ + +#define SBI_EXT_SRST_SYS_RESET 0x0 + +/* SBI system reset type */ + +#define SBI_SRST_TYPE_SHUTDOWN 0 +#define SBI_SRST_TYPE_REBOOT_COLD 1 +#define SBI_SRST_TYPE_REBOOT_WARM 1 + +/* SBI system reset reason */ + +#define SBI_SRST_REASON_NONE 0 +#define SBI_SRST_REASON_FAILURE 1 + /**************************************************************************** * Public Types ****************************************************************************/ @@ -335,6 +351,7 @@ void riscv_sbi_set_timer(uint64_t stime_value); uint64_t riscv_sbi_get_time(void); uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr, uintptr_t a1); +uintptr_t riscv_sbi_system_reset(uint32_t type, uint32_t reason); #endif /* Power management *********************************************************/ diff --git a/arch/risc-v/src/common/supervisor/riscv_sbi.c b/arch/risc-v/src/common/supervisor/riscv_sbi.c index da2e4c2dc0..865a4a6f9c 100644 --- a/arch/risc-v/src/common/supervisor/riscv_sbi.c +++ b/arch/risc-v/src/common/supervisor/riscv_sbi.c @@ -128,14 +128,20 @@ uint64_t riscv_sbi_get_time(void) uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase) { return sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, - hmask, hbase, 0, 0, 0, 0); + hmask, hbase, 0, 0, 0, 0); } #ifndef CONFIG_NUTTSBI +uintptr_t riscv_sbi_system_reset(uint32_t type, uint32_t reason) +{ + return sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_SYS_RESET, + type, reason, 0, 0, 0, 0); +} + uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr, uintptr_t a1) { return sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START, - hartid, addr, a1, 0, 0, 0); + hartid, addr, a1, 0, 0, 0); } #endif /* CONFIG_NUTTSBI */
