This is an automated email from the ASF dual-hosted git repository. masayuki pushed a commit to branch revert-12265-static-idlestack in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit c135b0b8b5ca6ca283ad5ef25c814e3b4c593199 Author: Masayuki Ishikawa <[email protected]> AuthorDate: Sun May 12 08:43:50 2024 +0900 Revert "arch/risc-v: remove g_cpux_idlestack" This reverts commit bc022f8cd841b6b9f6507b7aca6abbab931345b3. --- arch/risc-v/src/bl602/bl602_start.c | 4 ++++ arch/risc-v/src/bl808/bl808_start.c | 4 ++++ arch/risc-v/src/c906/c906_start.c | 4 ++++ arch/risc-v/src/common/espressif/esp_start.c | 4 ++++ arch/risc-v/src/common/riscv_common_memorymap.h | 3 +-- arch/risc-v/src/common/riscv_cpuidlestack.c | 4 +++- arch/risc-v/src/common/riscv_initialstate.c | 2 +- arch/risc-v/src/common/riscv_internal.h | 12 ++++++++++++ arch/risc-v/src/esp32c3-legacy/esp32c3_start.c | 4 ++++ arch/risc-v/src/fe310/fe310_start.c | 4 ++++ arch/risc-v/src/hpm6000/hpm_start.c | 4 ++++ arch/risc-v/src/hpm6750/hpm6750_start.c | 4 ++++ arch/risc-v/src/jh7110/jh7110_start.c | 4 ++++ arch/risc-v/src/k210/k210_start.c | 4 ++++ arch/risc-v/src/k230/k230_start.c | 2 ++ arch/risc-v/src/litex/litex_start.c | 4 ++++ arch/risc-v/src/mpfs/mpfs_start.c | 4 ++++ arch/risc-v/src/qemu-rv/qemu_rv_start.c | 2 ++ arch/risc-v/src/rv32m1/rv32m1_start.c | 4 ++++ 19 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c index 104a72bc2f..63e99b6dec 100644 --- a/arch/risc-v/src/bl602/bl602_start.c +++ b/arch/risc-v/src/bl602/bl602_start.c @@ -148,6 +148,10 @@ void bfl_main(void) asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2)); + /* Setup base stack */ + + riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE); + /* Configure the UART so we can get debug output */ bl602_lowsetup(); diff --git a/arch/risc-v/src/bl808/bl808_start.c b/arch/risc-v/src/bl808/bl808_start.c index 7e0663b603..d882f0671b 100644 --- a/arch/risc-v/src/bl808/bl808_start.c +++ b/arch/risc-v/src/bl808/bl808_start.c @@ -267,6 +267,10 @@ void bl808_start(int mhartid) bl808_clear_bss(); + /* Setup base stack */ + + riscv_set_basestack(BL808_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Copy the RAM Disk */ bl808_copy_ramdisk(); diff --git a/arch/risc-v/src/c906/c906_start.c b/arch/risc-v/src/c906/c906_start.c index a6ec7d9d38..d4774a2a01 100644 --- a/arch/risc-v/src/c906/c906_start.c +++ b/arch/risc-v/src/c906/c906_start.c @@ -79,6 +79,10 @@ void __c906_start(uint32_t mhartid) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(C906_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/common/espressif/esp_start.c b/arch/risc-v/src/common/espressif/esp_start.c index 7ad3c87da8..28c33c53c3 100644 --- a/arch/risc-v/src/common/espressif/esp_start.c +++ b/arch/risc-v/src/common/espressif/esp_start.c @@ -453,6 +453,10 @@ void __esp_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE); + /* Setup the syscall table needed by the ROM code */ esp_setup_syscall_table(); diff --git a/arch/risc-v/src/common/riscv_common_memorymap.h b/arch/risc-v/src/common/riscv_common_memorymap.h index efe3e050d6..c80382d0e0 100644 --- a/arch/risc-v/src/common/riscv_common_memorymap.h +++ b/arch/risc-v/src/common/riscv_common_memorymap.h @@ -67,8 +67,7 @@ EXTERN uintptr_t g_idle_topstack; /* Address of per-cpu idle stack base */ -#define g_cpux_idlestack(cpuid) \ - (g_idle_topstack - SMP_STACK_SIZE * ((cpuid) + 1)) +EXTERN const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS]; /* Address of the saved user stack pointer */ diff --git a/arch/risc-v/src/common/riscv_cpuidlestack.c b/arch/risc-v/src/common/riscv_cpuidlestack.c index 6bde88ace6..18f211bfda 100644 --- a/arch/risc-v/src/common/riscv_cpuidlestack.c +++ b/arch/risc-v/src/common/riscv_cpuidlestack.c @@ -50,6 +50,8 @@ uintptr_t g_idle_topstack = (uintptr_t)_ebss + SMP_STACK_SIZE * CONFIG_SMP_NCPUS; +const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -107,7 +109,7 @@ int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) /* Get the top of the stack */ - stack_alloc = (uintptr_t)g_cpux_idlestack(cpu); + stack_alloc = (uintptr_t)g_cpux_idlestack[cpu]; DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc)); tcb->adj_stack_size = SMP_STACK_SIZE; diff --git a/arch/risc-v/src/common/riscv_initialstate.c b/arch/risc-v/src/common/riscv_initialstate.c index f13203a519..0fd258404a 100644 --- a/arch/risc-v/src/common/riscv_initialstate.c +++ b/arch/risc-v/src/common/riscv_initialstate.c @@ -97,7 +97,7 @@ void up_initial_state(struct tcb_s *tcb) if (tcb->pid == IDLE_PROCESS_ID) { - tcb->stack_alloc_ptr = (void *)g_cpux_idlestack(riscv_mhartid()); + tcb->stack_alloc_ptr = (void *)g_cpux_idlestack[riscv_mhartid()]; tcb->stack_base_ptr = tcb->stack_alloc_ptr; tcb->adj_stack_size = SMP_STACK_SIZE; diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index d2a09e456e..c54c8b3fea 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -331,6 +331,18 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size); int riscv_configured_pmp_regions(void); int riscv_next_free_pmp_region(void); +/* RISC-V Memorymap Config **************************************************/ + +static inline void riscv_set_basestack(uintptr_t base, uintptr_t size) +{ + unsigned int i; + + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + g_cpux_idlestack[i] = (const uint8_t *)(base + size * i); + } +} + /* RISC-V SBI wrappers ******************************************************/ #ifdef CONFIG_ARCH_USE_S_MODE diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c index 29f5dc9feb..ae808190f9 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c @@ -288,6 +288,10 @@ void __esp32c3_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack((uintptr_t)_ebss, SMP_STACK_SIZE); + /* Setup the syscall table needed by the ROM code */ setup_syscall_table(); diff --git a/arch/risc-v/src/fe310/fe310_start.c b/arch/risc-v/src/fe310/fe310_start.c index 885ea5b3d0..7e08910d3f 100644 --- a/arch/risc-v/src/fe310/fe310_start.c +++ b/arch/risc-v/src/fe310/fe310_start.c @@ -69,6 +69,10 @@ void __fe310_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(FE310_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/hpm6000/hpm_start.c b/arch/risc-v/src/hpm6000/hpm_start.c index 051249c066..331e5d2098 100644 --- a/arch/risc-v/src/hpm6000/hpm_start.c +++ b/arch/risc-v/src/hpm6000/hpm_start.c @@ -64,6 +64,10 @@ void __hpm_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(HPM_IDLESTACK_BASE, CONFIG_IDLETHREAD_STACKSIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/hpm6750/hpm6750_start.c b/arch/risc-v/src/hpm6750/hpm6750_start.c index 7afdaed2fe..108fe5ff28 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_start.c +++ b/arch/risc-v/src/hpm6750/hpm6750_start.c @@ -64,6 +64,10 @@ void __hpm6750_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(HPM6750_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/jh7110/jh7110_start.c b/arch/risc-v/src/jh7110/jh7110_start.c index a55844ffa1..334bac41fa 100644 --- a/arch/risc-v/src/jh7110/jh7110_start.c +++ b/arch/risc-v/src/jh7110/jh7110_start.c @@ -133,6 +133,10 @@ void jh7110_start(int mhartid) { jh7110_clear_bss(); + /* Setup base stack */ + + riscv_set_basestack(JH7110_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Initialize the per CPU areas */ riscv_percpu_add_hart(mhartid); diff --git a/arch/risc-v/src/k210/k210_start.c b/arch/risc-v/src/k210/k210_start.c index 65855c55a5..7d3fa35e03 100644 --- a/arch/risc-v/src/k210/k210_start.c +++ b/arch/risc-v/src/k210/k210_start.c @@ -79,6 +79,10 @@ void __k210_start(uint32_t mhartid) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(K210_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/k230/k230_start.c b/arch/risc-v/src/k230/k230_start.c index abc378188c..a389558f3c 100644 --- a/arch/risc-v/src/k230/k230_start.c +++ b/arch/risc-v/src/k230/k230_start.c @@ -115,6 +115,8 @@ void k230_start(int mhartid, const char *dtb) { k230_clear_bss(); + riscv_set_basestack(K230_IDLESTACK_BASE, SMP_STACK_SIZE); + #ifdef CONFIG_RISCV_PERCPU_SCRATCH riscv_percpu_add_hart(mhartid); #else diff --git a/arch/risc-v/src/litex/litex_start.c b/arch/risc-v/src/litex/litex_start.c index a3107a40a7..8d5c0b6531 100644 --- a/arch/risc-v/src/litex/litex_start.c +++ b/arch/risc-v/src/litex/litex_start.c @@ -81,6 +81,10 @@ void __litex_start(int hart_index, const void * fdt, int arg) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(LITEX_IDLESTACK_BASE, SMP_STACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/mpfs/mpfs_start.c b/arch/risc-v/src/mpfs/mpfs_start.c index 1b92822472..02b74cec06 100644 --- a/arch/risc-v/src/mpfs/mpfs_start.c +++ b/arch/risc-v/src/mpfs/mpfs_start.c @@ -86,6 +86,10 @@ void __mpfs_start(uint64_t mhartid) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(MPFS_IDLESTACK_BASE, MPFS_IDLESTACK_SIZE); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c index c9d9bf736b..6335562beb 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_start.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_start.c @@ -140,6 +140,8 @@ void qemu_rv_start(int mhartid, const char *dtb) qemu_rv_clear_bss(); + riscv_set_basestack(QEMU_RV_IDLESTACK_BASE, SMP_STACK_SIZE); + #ifdef CONFIG_RISCV_PERCPU_SCRATCH riscv_percpu_add_hart(mhartid); #endif diff --git a/arch/risc-v/src/rv32m1/rv32m1_start.c b/arch/risc-v/src/rv32m1/rv32m1_start.c index c6ae0926d5..2a841ddebe 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_start.c +++ b/arch/risc-v/src/rv32m1/rv32m1_start.c @@ -101,6 +101,10 @@ void __rv32m1_start(void) *dest++ = 0; } + /* Setup base stack */ + + riscv_set_basestack(RV32M1_IDLESTACK_BASE, RV32M1_IDLESTACK_TOP); + /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the
