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The following commit(s) were added to refs/heads/master by this push:
new d0210c1174 riscv_tcbinfo: Fix register ordering for PC
d0210c1174 is described below
commit d0210c1174f4b25e21987e56cf4d65cf977e983d
Author: Huang Qi <[email protected]>
AuthorDate: Mon Jul 8 17:30:42 2024 +0800
riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't
existed in thread context, use any other register for it, and its value will be
omitted by gdb client.
Signed-off-by: Huang Qi <[email protected]>
---
arch/risc-v/src/common/riscv_tcbinfo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/common/riscv_tcbinfo.c
b/arch/risc-v/src/common/riscv_tcbinfo.c
index 1ad6216243..52e0b9c875 100644
--- a/arch/risc-v/src/common/riscv_tcbinfo.c
+++ b/arch/risc-v/src/common/riscv_tcbinfo.c
@@ -34,7 +34,7 @@
static const uint16_t g_reg_offs[] =
{
- TCB_REG_OFF(REG_EPC_NDX),
+ TCB_REG_OFF(REG_EPC_NDX), /* X0, but it will be ommited by gdb client */
TCB_REG_OFF(REG_X1_NDX),
TCB_REG_OFF(REG_X2_NDX),
TCB_REG_OFF(REG_X3_NDX),
@@ -66,6 +66,7 @@ static const uint16_t g_reg_offs[] =
TCB_REG_OFF(REG_X29_NDX),
TCB_REG_OFF(REG_X30_NDX),
TCB_REG_OFF(REG_X31_NDX),
+ TCB_REG_OFF(REG_EPC_NDX),
#if 0
# ifdef CONFIG_ARCH_FPU
