no1wudi commented on code in PR #12554: URL: https://github.com/apache/nuttx/pull/12554#discussion_r1671711771
########## arch/risc-v/src/common/riscv_debug.c: ########## @@ -0,0 +1,381 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_debug.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Notice: + * + * This driver is based on the RISC-V Debug Specification, version 0.13.2. + * The latest version of the specification can be found at: + * https://github.com/riscv/riscv-debug-spec + * + * The 1.0 version of the specification is still in RC phase, so there are + * no chips that support it yet. The 0.13.2 version is the latest stable + * version and some chips support it (e.g. QEMU RV, ESP32C3, BL602 etc). + * + * So this driver may needs to be updated when there is a new chip that + * supports the 1.0 version of the specification. + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> + +#include <arch/chip/chip.h> +#include <arch/csr.h> + +#include <stdbool.h> + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check the essential definition that must from chip vendor */ + +#ifndef RISCV_DEBUG_NR_TRIGGER +# error "Number of trigger in debug module is missing" +#endif + +/* CSR bits for TCONTROL */ + +#define TCONTROL_MTE (1 << 3) /* M-mode trigger enable */ Review Comment: Yes, but if no one else is paying attention to these definitions, then this is not an issue ? Moreover, only a few bit definitions have been added at the moment and consider the version control (debug spec 0.13 and future 1.0), will make the csr.h difficult to maintain. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
