acassis commented on code in PR #12804: URL: https://github.com/apache/nuttx/pull/12804#discussion_r1697176084
########## arch/risc-v/include/csr.h: ########## @@ -390,6 +390,27 @@ #define MISELECT_CLICINTIE 0x1400 /* MIREG2 */ #define MISELECT_CLICINTTRIG 0x1480 /* MIREG */ +/* AIA Machine-Level CSRs */ Review Comment: Please include an empty line after comment lines. No idea why checkpatch didn't get it. ########## arch/risc-v/include/csr.h: ########## @@ -390,6 +390,27 @@ #define MISELECT_CLICINTIE 0x1400 /* MIREG2 */ #define MISELECT_CLICINTTRIG 0x1480 /* MIREG */ +/* AIA Machine-Level CSRs */ +#define CSR_MTOPEI 0x35c /* Machine top external interrupt */ +#define CSR_MTOPI 0xfb0 /* Machine top interrupt */ +#define CSR_MVIEN 0x308 /* Machine virtual interrupt enables */ +#define CSR_MVIP 0x309 /* Machine virtual interrupt-pending bits */ + +/* AIA Machine-Level CSRs (High-Half) */ Review Comment: Ditto ########## arch/risc-v/src/common/riscv_aia.h: ########## @@ -0,0 +1,288 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_aia.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H +#define __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/bits.h> +#include <arch/csr.h> +#include "riscv_internal.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AIA IMSIC */ Review Comment: Ditto ########## arch/risc-v/src/common/riscv_aia.h: ########## @@ -0,0 +1,288 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_aia.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H +#define __ARCH_RISCV_SRC_COMMON_RISCV_AIA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/bits.h> +#include <arch/csr.h> +#include "riscv_internal.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AIA IMSIC */ +#define RISCV_IMSIC_MAX_REGS 16 + +#define RISCV_IMSIC_MMIO_PAGE_LE 0x00 +#define RISCV_IMSIC_MMIO_PAGE_BE 0x04 +#define RISCV_IMSIC_MMIO_PAGE_BIT 12 + +#define RISCV_IMSIC_TOPEI_ID_BIT 16 + +#define RISCV_IMSIC_EIP_BITS 32 +#define RISCV_IMSIC_EIE_BITS 32 + +#define RISCV_IMSIC_DISABLE_EIDELIVERY 0 +#define RISCV_IMSIC_ENABLE_EIDELIVERY 1 +#define RISCV_IMSIC_DISABLE_EITHRESHOLD 1 +#define RISCV_IMSIC_ENABLE_EITHRESHOLD 0 + +#define RISCV_IMSIC_IPI_ID 1 + +/* AIA APLIC */ Review Comment: Diito ########## arch/risc-v/include/csr.h: ########## @@ -390,6 +390,27 @@ #define MISELECT_CLICINTIE 0x1400 /* MIREG2 */ #define MISELECT_CLICINTTRIG 0x1480 /* MIREG */ +/* AIA Machine-Level CSRs */ +#define CSR_MTOPEI 0x35c /* Machine top external interrupt */ +#define CSR_MTOPI 0xfb0 /* Machine top interrupt */ +#define CSR_MVIEN 0x308 /* Machine virtual interrupt enables */ +#define CSR_MVIP 0x309 /* Machine virtual interrupt-pending bits */ + +/* AIA Machine-Level CSRs (High-Half) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + +/* AIA Supervisor-Level CSRs */ +#define CSR_STOPEI 0x15c /* Supervisor top external interrupt */ +#define CSR_STOPI 0xdb0 /* Supervisor top interrupt */ + +/* AIA Supervisor-Level CSRs (High-Half) */ Review Comment: Ditto ########## arch/risc-v/include/csr.h: ########## @@ -390,6 +390,27 @@ #define MISELECT_CLICINTIE 0x1400 /* MIREG2 */ #define MISELECT_CLICINTTRIG 0x1480 /* MIREG */ +/* AIA Machine-Level CSRs */ +#define CSR_MTOPEI 0x35c /* Machine top external interrupt */ +#define CSR_MTOPI 0xfb0 /* Machine top interrupt */ +#define CSR_MVIEN 0x308 /* Machine virtual interrupt enables */ +#define CSR_MVIP 0x309 /* Machine virtual interrupt-pending bits */ + +/* AIA Machine-Level CSRs (High-Half) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + +/* AIA Supervisor-Level CSRs */ Review Comment: Ditto ########## arch/risc-v/include/csr.h: ########## @@ -554,6 +575,159 @@ #define COUNTEREN_HPM30 (0x1 << 30) #define COUNTEREN_HPM31 (0x1 << 31) +/* In topi/topei register */ +#define TOPI_IID_SHIFT 16 +#define TOPI_IPRIO_BITS 8 +#define TOPEI_ID_SHIFT 16 + +/* In iselect register (AIA) */ Review Comment: Ditto ########## arch/risc-v/include/csr.h: ########## @@ -554,6 +575,159 @@ #define COUNTEREN_HPM30 (0x1 << 30) #define COUNTEREN_HPM31 (0x1 << 31) +/* In topi/topei register */ Review Comment: Ditto -- This is an automated message from the Apache Git Service. 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