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new 75c65c7ce9 arch/stm32h7: add defines for USART clock selection
75c65c7ce9 is described below
commit 75c65c7ce93d58f5a783a33e6f13183bd2f5924b
Author: Julian Oes <[email protected]>
AuthorDate: Tue Aug 6 13:36:50 2024 +1200
arch/stm32h7: add defines for USART clock selection
This adds the necessary defines to set the USARTs' kernel clock source
selection.
This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.
This is according to the reference manual RM0399 page 448.
---
arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h | 13 +++++++++++++
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 18 ++++++++++++++++++
arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 17 +++++++++++++++++
3 files changed, 48 insertions(+)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
index 1c0de2d453..1c88a5cb13 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
@@ -568,8 +568,21 @@
#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */
# define RCC_D2CCIP2R_USART234578SEL_MASK (7 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_RCC (0 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_PLL2 (1 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_PLL3 (2 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_HSI (3 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_CSI (4 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
+# define RCC_D2CCIP2R_USART234578SEL_LSE (5 <<
RCC_D2CCIP2R_USART234578SEL_SHIFT)
#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */
# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_RCC (0 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_PLL2 (1 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_PLL3 (2 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_HSI (3 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_CSI (4 << RCC_D2CCIP2R_USART16SEL_SHIFT)
+# define RCC_D2CCIP2R_USART16SEL_LSE (5 << RCC_D2CCIP2R_USART16SEL_SHIFT)
/* Bits 6-7: Reserved */
#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */
# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT)
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index 5543c7ede6..da7af1f59c 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -1024,6 +1024,24 @@ void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_D2CCIP2R);
#endif
+ /* Configure USART2, 3, 4, 5, 7, and 8 kernel clock source selection */
+
+#if defined(STM32_RCC_D2CCIP2R_USART234578_SEL)
+ regval = getreg32(STM32_RCC_D2CCIP2R);
+ regval &= ~RCC_D2CCIP2R_USART234578SEL_MASK;
+ regval |= STM32_RCC_D2CCIP2R_USART234578_SEL;
+ putreg32(regval, STM32_RCC_D2CCIP2R);
+#endif
+
+ /* Configure USART1 and 6 kernel clock source selection */
+
+#if defined(STM32_RCC_D2CCIP2R_USART16_SEL)
+ regval = getreg32(STM32_RCC_D2CCIP2R);
+ regval &= ~RCC_D2CCIP2R_USART16SEL_MASK;
+ regval |= STM32_RCC_D2CCIP2R_USART16_SEL;
+ putreg32(regval, STM32_RCC_D2CCIP2R);
+#endif
+
/* Configure ADC source clock */
#if defined(STM32_RCC_D3CCIPR_ADCSRC)
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index 813c523797..f1d9702a19 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -993,6 +993,23 @@ void stm32_stdclockconfig(void)
regval |= STM32_RCC_D2CCIP2R_USBSRC;
putreg32(regval, STM32_RCC_D2CCIP2R);
#endif
+ /* Configure USART2, 3, 4, 5, 7, and 8 kernel clock source selection */
+
+#if defined(STM32_RCC_D2CCIP2R_USART234578_SEL)
+ regval = getreg32(STM32_RCC_D2CCIP2R);
+ regval &= ~RCC_D2CCIP2R_USART234578SEL_MASK;
+ regval |= STM32_RCC_D2CCIP2R_USART234578_SEL;
+ putreg32(regval, STM32_RCC_D2CCIP2R);
+#endif
+
+ /* Configure USART1 and 6 kernel clock source selection */
+
+#if defined(STM32_RCC_D2CCIP2R_USART16_SEL)
+ regval = getreg32(STM32_RCC_D2CCIP2R);
+ regval &= ~RCC_D2CCIP2R_USART16SEL_MASK;
+ regval |= STM32_RCC_D2CCIP2R_USART16_SEL;
+ putreg32(regval, STM32_RCC_D2CCIP2R);
+#endif
/* Configure ADC source clock */
