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new b14dc8f8ae risc-v/mmu: Configure T-Head MMU to cache User Text, Data
and Heap
b14dc8f8ae is described below
commit b14dc8f8ae71b30b6c2763977100d078a5b0c42f
Author: Lup Yuen Lee <[email protected]>
AuthorDate: Mon Aug 26 15:08:40 2024 +0800
risc-v/mmu: Configure T-Head MMU to cache User Text, Data and Heap
This PR configures the T-Head MMU to cache the the User Text, Data and
Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as
explained in this article:
https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906
This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000
SoCs: https://github.com/apache/nuttx/issues/12696. With this fix, SG2000 NuttX
CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark)
We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable
T-Head MMU extension support"). Enabling this Kconfig Option will configure the
T-Head MMU to cache the User Text, Data and Heap.
This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The
next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).
Modified Files:
`arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will
configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC.
`arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable,
Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD`
is enabled
`arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32
bits to 64 bits, to accommodate the T-Head MMU Flags
`arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32
bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only
for MMU Paging (`CONFIG_PAGING`).
---
arch/risc-v/Kconfig | 8 ++++++++
arch/risc-v/src/common/riscv_addrenv.c | 2 +-
arch/risc-v/src/common/riscv_exception.c | 2 +-
arch/risc-v/src/common/riscv_mmu.h | 20 ++++++++++++++++++--
4 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index 4982e57cd8..ed89a17ad5 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -336,6 +336,7 @@ config ARCH_CHIP_SG2000
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MPU
select ARCH_MMU_TYPE_SV39
+ select ARCH_MMU_EXT_THEAD
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_S_MODE
@@ -516,6 +517,13 @@ config ARCH_MMU_TYPE_SV32
default n
select ARCH_HAVE_MMU
+config ARCH_MMU_EXT_THEAD
+ bool "Enable T-Head MMU extension support"
+ default n
+ depends on ARCH_HAVE_MMU
+ ---help---
+ Enable support for T-Head MMU extension.
+
config ARCH_HAVE_S_MODE
bool
default n
diff --git a/arch/risc-v/src/common/riscv_addrenv.c
b/arch/risc-v/src/common/riscv_addrenv.c
index 20695ed1e6..4e3afd1bce 100644
--- a/arch/risc-v/src/common/riscv_addrenv.c
+++ b/arch/risc-v/src/common/riscv_addrenv.c
@@ -231,7 +231,7 @@ static int copy_kernel_mappings(arch_addrenv_t *addrenv)
****************************************************************************/
static int create_region(arch_addrenv_t *addrenv, uintptr_t vaddr,
- size_t size, uint32_t mmuflags)
+ size_t size, uint64_t mmuflags)
{
uintptr_t ptlast;
uintptr_t ptprev;
diff --git a/arch/risc-v/src/common/riscv_exception.c
b/arch/risc-v/src/common/riscv_exception.c
index 1666d334ef..e3ed15ee37 100644
--- a/arch/risc-v/src/common/riscv_exception.c
+++ b/arch/risc-v/src/common/riscv_exception.c
@@ -177,7 +177,7 @@ int riscv_fillpage(int mcause, void *regs, void *args)
uintptr_t vaddr;
uint32_t ptlevel;
uintptr_t satp;
- uint32_t mmuflags;
+ uint64_t mmuflags;
_info("EXCEPTION: %s. MCAUSE: %" PRIxREG ", EPC: %" PRIxREG
", MTVAL: %" PRIxREG "\n",
diff --git a/arch/risc-v/src/common/riscv_mmu.h
b/arch/risc-v/src/common/riscv_mmu.h
index a2cd9f0ee2..96ab0c038e 100644
--- a/arch/risc-v/src/common/riscv_mmu.h
+++ b/arch/risc-v/src/common/riscv_mmu.h
@@ -46,6 +46,22 @@
#define PTE_A (1 << 6) /* Page has been accessed */
#define PTE_D (1 << 7) /* Page is dirty */
+/* T-Head MMU needs Text and Data to be Shareable, Bufferable, Cacheable */
+
+#ifdef CONFIG_ARCH_MMU_EXT_THEAD
+# define PTE_SEC (1UL << 59) /* Security */
+# define PTE_SHARE (1UL << 60) /* Shareable */
+# define PTE_BUF (1UL << 61) /* Bufferable */
+# define PTE_CACHE (1UL << 62) /* Cacheable */
+# define PTE_SO (1UL << 63) /* Strong Order */
+
+# define EXT_UTEXT_FLAGS (PTE_SHARE | PTE_BUF | PTE_CACHE)
+# define EXT_UDATA_FLAGS (PTE_SHARE | PTE_BUF | PTE_CACHE)
+#else
+# define EXT_UTEXT_FLAGS (0)
+# define EXT_UDATA_FLAGS (0)
+#endif
+
/* Check if leaf PTE entry or not (if X/W/R are set it is) */
#define PTE_LEAF_MASK (7 << 1)
@@ -56,8 +72,8 @@
/* Flags for user FLASH (RX) and user RAM (RW) */
-#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U)
-#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U)
+#define MMU_UTEXT_FLAGS (PTE_R | PTE_X | PTE_U | EXT_UTEXT_FLAGS)
+#define MMU_UDATA_FLAGS (PTE_R | PTE_W | PTE_U | EXT_UDATA_FLAGS)
/* I/O region flags */
