(nuttx) branch master updated: risc-v: Add a new option to control exception reason

[acassis]

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acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 6695affe87 risc-v: Add a new option to control exception reason
6695affe87 is described below

commit 6695affe87a521536c7360483cfbf6158dfbe1dc
Author: Huang Qi <huang...@xiaomi.com>
AuthorDate: Tue Sep 17 20:39:40 2024 +0800

    risc-v: Add a new option to control exception reason
    
    The number of exception for risc-v is 16 (0 ~ 15)
    for the machine ISA version 1.12 or earlier, the number of exception is 20
    (0 ~ 19) from the ISA version 1.13. And maybe changed in the future.
    
    Using a dedicated option to control the exception number to allow the 
earlier
    version chip with customized exception number (e.g. 16 ~ 19 used) to define
    the exception reason string correctly.
    
    Signed-off-by: Huang Qi <huang...@xiaomi.com>
---
 arch/risc-v/Kconfig                      | 8 ++++++++
 arch/risc-v/src/common/riscv_exception.c | 8 +-------
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index fbd2a7878f..052954b6d0 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -403,6 +403,14 @@ config ARCH_RV_VECTOR_BYTE_LENGTH
 
 endif
 
+config ARCH_RV_MACHINE_ISA_1_13
+       bool "Machine ISA Version 1.13 or later"
+       default n
+       ---help---
+               Indicates support for Machine ISA Version 1.13 or later.
+               This version defined hardware error and software check 
exception codes,
+               which extend the range of exception codes from 0 ~ 15 to 0 ~ 19.
+
 config ARCH_RV_ISA_ZICSR_ZIFENCEI
        bool
        default y
diff --git a/arch/risc-v/src/common/riscv_exception.c 
b/arch/risc-v/src/common/riscv_exception.c
index 9aa3273e4a..e77a3c8ee8 100644
--- a/arch/risc-v/src/common/riscv_exception.c
+++ b/arch/risc-v/src/common/riscv_exception.c
@@ -65,16 +65,10 @@ static const char *g_reasons_str[RISCV_MAX_EXCEPTION + 1] =
   "Load page fault",
   "Reserved",
   "Store/AMO page fault",
-#if RISCV_MAX_EXCEPTION > 15
+#ifdef CONFIG_ARCH_RV_MACHINE_ISA_1_13
   "Reserved",
-#endif
-#if RISCV_MAX_EXCEPTION > 16
   "Reserved",
-#endif
-#if RISCV_MAX_EXCEPTION > 17
   "Software check",
-#endif
-#if RISCV_MAX_EXCEPTION > 18
   "Hardware error",
 #endif
 #ifdef RISCV_CUSTOM_EXCEPTION_REASONS