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The following commit(s) were added to refs/heads/master by this push:
new f68d594420 arch/arm64: rename register names to align with arm32
f68d594420 is described below
commit f68d5944201b43de775a6eaa9c4b6db2f4228796
Author: Xu Xingliang <[email protected]>
AuthorDate: Tue Apr 23 21:10:57 2024 +0800
arch/arm64: rename register names to align with arm32
Signed-off-by: Xu Xingliang <[email protected]>
Signed-off-by: lipengfei28 <[email protected]>
---
arch/arm64/include/irq.h | 85 ++++++++++++++++--------------
arch/arm64/src/common/arm64_copystate.c | 10 ++--
arch/arm64/src/common/arm64_fork.h | 2 +-
arch/arm64/src/common/arm64_fpu.c | 6 +--
arch/arm64/src/common/arm64_fpu_func.S | 64 +++++++++++-----------
arch/arm64/src/common/arm64_vector_table.S | 6 +--
6 files changed, 89 insertions(+), 84 deletions(-)
diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h
index 65ec6716af..42a00c2066 100644
--- a/arch/arm64/include/irq.h
+++ b/arch/arm64/include/irq.h
@@ -149,8 +149,8 @@
/* In Armv8-A Architecture, the stack must align with 16 byte */
-#define XCPTCONTEXT_GP_REGS (36)
-#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+#define ARM64_CONTEXT_REGS (38)
+#define ARM64_CONTEXT_SIZE (8 * ARM64_CONTEXT_REGS)
#ifdef CONFIG_ARCH_FPU
@@ -166,59 +166,64 @@
/* 128bit registers */
-#define FPU_REG_Q0 (0)
-#define FPU_REG_Q1 (1)
-#define FPU_REG_Q2 (2)
-#define FPU_REG_Q3 (3)
-#define FPU_REG_Q4 (4)
-#define FPU_REG_Q5 (5)
-#define FPU_REG_Q6 (6)
-#define FPU_REG_Q7 (7)
-#define FPU_REG_Q8 (8)
-#define FPU_REG_Q9 (9)
-#define FPU_REG_Q10 (10)
-#define FPU_REG_Q11 (11)
-#define FPU_REG_Q12 (12)
-#define FPU_REG_Q13 (13)
-#define FPU_REG_Q14 (14)
-#define FPU_REG_Q15 (15)
-#define FPU_REG_Q16 (16)
-#define FPU_REG_Q17 (17)
-#define FPU_REG_Q18 (18)
-#define FPU_REG_Q19 (19)
-#define FPU_REG_Q20 (20)
-#define FPU_REG_Q21 (21)
-#define FPU_REG_Q22 (22)
-#define FPU_REG_Q23 (23)
-#define FPU_REG_Q24 (24)
-#define FPU_REG_Q25 (25)
-#define FPU_REG_Q26 (26)
-#define FPU_REG_Q27 (27)
-#define FPU_REG_Q28 (28)
-#define FPU_REG_Q29 (29)
-#define FPU_REG_Q30 (30)
-#define FPU_REG_Q31 (31)
+#define REG_Q0 (0)
+#define REG_Q1 (1)
+#define REG_Q2 (2)
+#define REG_Q3 (3)
+#define REG_Q4 (4)
+#define REG_Q5 (5)
+#define REG_Q6 (6)
+#define REG_Q7 (7)
+#define REG_Q8 (8)
+#define REG_Q9 (9)
+#define REG_Q10 (10)
+#define REG_Q11 (11)
+#define REG_Q12 (12)
+#define REG_Q13 (13)
+#define REG_Q14 (14)
+#define REG_Q15 (15)
+#define REG_Q16 (16)
+#define REG_Q17 (17)
+#define REG_Q18 (18)
+#define REG_Q19 (19)
+#define REG_Q20 (20)
+#define REG_Q21 (21)
+#define REG_Q22 (22)
+#define REG_Q23 (23)
+#define REG_Q24 (24)
+#define REG_Q25 (25)
+#define REG_Q26 (26)
+#define REG_Q27 (27)
+#define REG_Q28 (28)
+#define REG_Q29 (29)
+#define REG_Q30 (30)
+#define REG_Q31 (31)
/* 32 bit registers
*/
-#define FPU_REG_FPSR (0)
-#define FPU_REG_FPCR (1)
+#define REG_FPSR (0)
+#define REG_FPCR (1)
/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
* FPU FPSR/SPSR(32 bit) : 1
* FPU TRAP: 1
* 64 + 1 + 1 = 66
*/
-#define XCPTCONTEXT_FPU_REGS (66)
+#define FPU_CONTEXT_REGS (66)
#else
-#define XCPTCONTEXT_FPU_REGS (0)
+#define FPU_CONTEXT_REGS (0)
#endif
-#define FPUCONTEXT_SIZE (8 * XCPTCONTEXT_FPU_REGS)
+#define FPU_CONTEXT_SIZE (8 * FPU_CONTEXT_REGS)
-#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
+#define XCPTCONTEXT_REGS (ARM64_CONTEXT_REGS + FPU_CONTEXT_REGS)
#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+/* Friendly register names */
+
+#define REG_FP REG_X29
+#define REG_LR REG_X30
+
#ifdef CONFIG_ARM64_DECODEFIQ
# define IRQ_DAIF_MASK (3)
#else
diff --git a/arch/arm64/src/common/arm64_copystate.c
b/arch/arm64/src/common/arm64_copystate.c
index 4d06f2ddaf..a59feda13c 100644
--- a/arch/arm64/src/common/arm64_copystate.c
+++ b/arch/arm64/src/common/arm64_copystate.c
@@ -67,7 +67,7 @@ int arch_save_fpucontext(void *saveregs)
flags = enter_critical_section();
- p_save = (uintptr_t)saveregs + XCPTCONTEXT_GP_SIZE;
+ p_save = (uintptr_t)saveregs + ARM64_CONTEXT_SIZE;
arm64_fpu_save((struct fpu_reg *)p_save);
ARM64_DSB();
@@ -95,14 +95,14 @@ int arm64_syscall_save_context(uint64_t * regs)
p_save = (uint64_t *)f_regs->regs[REG_X2];
- for (i = 0; i < XCPTCONTEXT_GP_REGS; i++)
+ for (i = 0; i < ARM64_CONTEXT_REGS; i++)
{
p_save[i] = regs[i];
}
#ifdef CONFIG_ARCH_FPU
rtcb = (struct tcb_s *)f_regs->regs[REG_X1];
- p_save += XCPTCONTEXT_GP_REGS;
+ p_save += ARM64_CONTEXT_SIZE;
if (rtcb_cur == rtcb)
{
arch_save_fpucontext(p_save);
@@ -110,8 +110,8 @@ int arm64_syscall_save_context(uint64_t * regs)
else
{
p_fpu = (uint64_t *)rtcb->xcp.regs;
- p_fpu += XCPTCONTEXT_GP_REGS;
- for (i = 0; i < XCPTCONTEXT_FPU_REGS; i++)
+ p_fpu += ARM64_CONTEXT_REGS;
+ for (i = 0; i < FPU_CONTEXT_REGS; i++)
{
p_save[i] = p_fpu[i];
}
diff --git a/arch/arm64/src/common/arm64_fork.h
b/arch/arm64/src/common/arm64_fork.h
index 2e4a5f5fde..b8bb5b8e6b 100644
--- a/arch/arm64/src/common/arm64_fork.h
+++ b/arch/arm64/src/common/arm64_fork.h
@@ -66,7 +66,7 @@
#define FORK_REG_SP (31) /* Stack pointer*/
#ifdef CONFIG_ARCH_FPU
-#define FORK_REGS_SIZE (32 + XCPTCONTEXT_FPU_REGS)
+#define FORK_REGS_SIZE (32 + FPU_CONTEXT_REGS)
#else
#define FORK_REGS_SIZE (32)
#endif
diff --git a/arch/arm64/src/common/arm64_fpu.c
b/arch/arm64/src/common/arm64_fpu.c
index e80e7240ae..7bd1885fd7 100644
--- a/arch/arm64/src/common/arm64_fpu.c
+++ b/arch/arm64/src/common/arm64_fpu.c
@@ -295,15 +295,15 @@ void arm64_fpu_disable(void)
bool up_fpucmp(const void *saveregs1, const void *saveregs2)
{
const uint64_t *regs1 = (uint64_t *)((uintptr_t)saveregs1 +
- XCPTCONTEXT_GP_SIZE);
+ ARM64_CONTEXT_SIZE);
const uint64_t *regs2 = (uint64_t *)((uintptr_t)saveregs2 +
- XCPTCONTEXT_GP_SIZE);
+ ARM64_CONTEXT_SIZE);
/* Only compare callee-saved registers, caller-saved registers do not
* need to be preserved.
*/
- return memcmp(®s1[FPU_REG_Q4], ®s2[FPU_REG_Q4],
+ return memcmp(®s1[REG_Q4], ®s2[REG_Q4],
8 * FPU_CALLEE_REGS) == 0;
}
diff --git a/arch/arm64/src/common/arm64_fpu_func.S
b/arch/arm64/src/common/arm64_fpu_func.S
index 13481ea098..de3f3d7e26 100644
--- a/arch/arm64/src/common/arm64_fpu_func.S
+++ b/arch/arm64/src/common/arm64_fpu_func.S
@@ -49,22 +49,22 @@
GTEXT(arm64_fpu_save)
SECTION_FUNC(text, arm64_fpu_save)
- stp q0, q1, [x0, #(16 * FPU_REG_Q0)]
- stp q2, q3, [x0, #(16 * FPU_REG_Q2)]
- stp q4, q5, [x0, #(16 * FPU_REG_Q4)]
- stp q6, q7, [x0, #(16 * FPU_REG_Q6)]
- stp q8, q9, [x0, #(16 * FPU_REG_Q8)]
- stp q10, q11, [x0, #(16 * FPU_REG_Q10)]
- stp q12, q13, [x0, #(16 * FPU_REG_Q12)]
- stp q14, q15, [x0, #(16 * FPU_REG_Q14)]
- stp q16, q17, [x0, #(16 * FPU_REG_Q16)]
- stp q18, q19, [x0, #(16 * FPU_REG_Q18)]
- stp q20, q21, [x0, #(16 * FPU_REG_Q20)]
- stp q22, q23, [x0, #(16 * FPU_REG_Q22)]
- stp q24, q25, [x0, #(16 * FPU_REG_Q24)]
- stp q26, q27, [x0, #(16 * FPU_REG_Q26)]
- stp q28, q29, [x0, #(16 * FPU_REG_Q28)]
- stp q30, q31, [x0, #(16 * FPU_REG_Q30)]
+ stp q0, q1, [x0, #(16 * REG_Q0)]
+ stp q2, q3, [x0, #(16 * REG_Q2)]
+ stp q4, q5, [x0, #(16 * REG_Q4)]
+ stp q6, q7, [x0, #(16 * REG_Q6)]
+ stp q8, q9, [x0, #(16 * REG_Q8)]
+ stp q10, q11, [x0, #(16 * REG_Q10)]
+ stp q12, q13, [x0, #(16 * REG_Q12)]
+ stp q14, q15, [x0, #(16 * REG_Q14)]
+ stp q16, q17, [x0, #(16 * REG_Q16)]
+ stp q18, q19, [x0, #(16 * REG_Q18)]
+ stp q20, q21, [x0, #(16 * REG_Q20)]
+ stp q22, q23, [x0, #(16 * REG_Q22)]
+ stp q24, q25, [x0, #(16 * REG_Q24)]
+ stp q26, q27, [x0, #(16 * REG_Q26)]
+ stp q28, q29, [x0, #(16 * REG_Q28)]
+ stp q30, q31, [x0, #(16 * REG_Q30)]
mrs x10, fpsr
mrs x11, fpcr
@@ -76,22 +76,22 @@ SECTION_FUNC(text, arm64_fpu_save)
GTEXT(arm64_fpu_restore)
SECTION_FUNC(text, arm64_fpu_restore)
- ldp q0, q1, [x0, #(16 * FPU_REG_Q0)]
- ldp q2, q3, [x0, #(16 * FPU_REG_Q2)]
- ldp q4, q5, [x0, #(16 * FPU_REG_Q4)]
- ldp q6, q7, [x0, #(16 * FPU_REG_Q6)]
- ldp q8, q9, [x0, #(16 * FPU_REG_Q8)]
- ldp q10, q11, [x0, #(16 * FPU_REG_Q10)]
- ldp q12, q13, [x0, #(16 * FPU_REG_Q12)]
- ldp q14, q15, [x0, #(16 * FPU_REG_Q14)]
- ldp q16, q17, [x0, #(16 * FPU_REG_Q16)]
- ldp q18, q19, [x0, #(16 * FPU_REG_Q18)]
- ldp q20, q21, [x0, #(16 * FPU_REG_Q20)]
- ldp q22, q23, [x0, #(16 * FPU_REG_Q22)]
- ldp q24, q25, [x0, #(16 * FPU_REG_Q24)]
- ldp q26, q27, [x0, #(16 * FPU_REG_Q26)]
- ldp q28, q29, [x0, #(16 * FPU_REG_Q28)]
- ldp q30, q31, [x0, #(16 * FPU_REG_Q30)]
+ ldp q0, q1, [x0, #(16 * REG_Q0)]
+ ldp q2, q3, [x0, #(16 * REG_Q2)]
+ ldp q4, q5, [x0, #(16 * REG_Q4)]
+ ldp q6, q7, [x0, #(16 * REG_Q6)]
+ ldp q8, q9, [x0, #(16 * REG_Q8)]
+ ldp q10, q11, [x0, #(16 * REG_Q10)]
+ ldp q12, q13, [x0, #(16 * REG_Q12)]
+ ldp q14, q15, [x0, #(16 * REG_Q14)]
+ ldp q16, q17, [x0, #(16 * REG_Q16)]
+ ldp q18, q19, [x0, #(16 * REG_Q18)]
+ ldp q20, q21, [x0, #(16 * REG_Q20)]
+ ldp q22, q23, [x0, #(16 * REG_Q22)]
+ ldp q24, q25, [x0, #(16 * REG_Q24)]
+ ldp q26, q27, [x0, #(16 * REG_Q26)]
+ ldp q28, q29, [x0, #(16 * REG_Q28)]
+ ldp q30, q31, [x0, #(16 * REG_Q30)]
ldr w10, [x0, #(16 * 32 + 0)]
ldr w11, [x0, #(16 * 32 + 4)]
diff --git a/arch/arm64/src/common/arm64_vector_table.S
b/arch/arm64/src/common/arm64_vector_table.S
index 8f58891c54..419b28b473 100644
--- a/arch/arm64/src/common/arm64_vector_table.S
+++ b/arch/arm64/src/common/arm64_vector_table.S
@@ -40,7 +40,7 @@
/* Save Corruptible Registers and exception context
* on the task stack
- * note: allocate stackframe with XCPTCONTEXT_GP_REGS
+ * note: allocate stackframe with ARM64_CONTEXT_REGS
* which is ARM64_ESF_REGS + ARM64_CS_REGS
* but only save ARM64_ESF_REGS
*/
@@ -92,7 +92,7 @@
/* Save the FPU registers */
#ifdef CONFIG_ARCH_FPU
- add x0, sp, #8 * XCPTCONTEXT_GP_REGS
+ add x0, sp, #8 * ARM64_CONTEXT_REGS
bl arm64_fpu_save
ldr x0, [sp, #8 * REG_X0]
#endif
@@ -250,7 +250,7 @@
SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
GTEXT(arm64_exit_exception)
SECTION_FUNC(text, arm64_exit_exception)
#ifdef CONFIG_ARCH_FPU
- add x0, sp, #8 * XCPTCONTEXT_GP_REGS
+ add x0, sp, #8 * ARM64_CONTEXT_REGS
bl arm64_fpu_restore
#endif
