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commit c35e25b7e561c5e87190dab86acf142dff12287d Author: hujun5 <[email protected]> AuthorDate: Thu Sep 19 21:41:40 2024 +0800 arch: rename xxxx_pause.c to xxxx_smpcall.c Signed-off-by: hujun5 <[email protected]> --- arch/arm/include/cxd56xx/irq.h | 2 +- arch/arm/include/lc823450/irq.h | 4 +-- arch/arm/include/rp2040/irq.h | 4 +-- arch/arm/include/sam34/sam4cm_irq.h | 4 +-- arch/arm/src/armv7-a/CMakeLists.txt | 2 +- arch/arm/src/armv7-a/Make.defs | 2 +- arch/arm/src/armv7-a/arm_gicv2.c | 26 ++--------------- .../arm_cpupause.c => armv7-a/arm_smpcall.c} | 33 +++++++++++++++++----- arch/arm/src/armv7-a/gic.h | 16 +++++------ arch/arm/src/armv7-r/CMakeLists.txt | 2 +- arch/arm/src/armv7-r/Make.defs | 2 +- arch/arm/src/armv7-r/arm_gicv2.c | 25 ++-------------- .../arm_cpupause.c => armv7-r/arm_smpcall.c} | 33 +++++++++++++++++----- arch/arm/src/armv7-r/gic.h | 16 +++++------ arch/arm/src/armv8-r/arm_gic.h | 12 ++++---- arch/arm/src/armv8-r/arm_gicv3.c | 30 +++----------------- arch/arm/src/cxd56xx/CMakeLists.txt | 2 +- arch/arm/src/cxd56xx/Make.defs | 2 +- arch/arm/src/cxd56xx/cxd56_cpustart.c | 10 +++---- arch/arm/src/cxd56xx/cxd56_irq.c | 2 +- .../cxd56xx/{cxd56_cpupause.c => cxd56_smpcall.c} | 20 +++++-------- arch/arm/src/lc823450/Make.defs | 2 +- arch/arm/src/lc823450/lc823450_cpustart.c | 10 +++---- .../{lc823450_cpupause.c => lc823450_smpcall.c} | 22 ++++++--------- arch/arm/src/rp2040/Make.defs | 2 +- arch/arm/src/rp2040/rp2040_cpustart.c | 10 +++---- arch/arm/src/rp2040/rp2040_irq.c | 4 +-- .../rp2040/{rp2040_cpupause.c => rp2040_smpcall.c} | 20 +++++-------- arch/arm/src/sam34/Make.defs | 2 +- arch/arm/src/sam34/sam4cm_cpustart.c | 10 +++---- .../sam34/{sam4cm_cpupause.c => sam4cm_smpcall.c} | 20 +++++-------- arch/arm64/src/common/CMakeLists.txt | 2 +- arch/arm64/src/common/Make.defs | 2 +- arch/arm64/src/common/arm64_gic.h | 20 ++++++------- arch/arm64/src/common/arm64_gicv2.c | 26 ++--------------- arch/arm64/src/common/arm64_gicv3.c | 31 +++----------------- .../common/{arm64_cpupause.c => arm64_smpcall.c} | 33 +++++++++++++++++----- arch/risc-v/src/common/CMakeLists.txt | 2 +- arch/risc-v/src/common/Make.defs | 2 +- arch/risc-v/src/common/riscv_exception.c | 2 +- arch/risc-v/src/common/riscv_internal.h | 2 +- .../common/{riscv_cpupause.c => riscv_smpcall.c} | 21 +++++--------- arch/risc-v/src/jh7110/jh7110_timerisr.c | 2 +- arch/sim/src/sim/sim_smpsignal.c | 21 ++++---------- arch/sparc/src/s698pm/Make.defs | 2 +- arch/sparc/src/s698pm/s698pm-irq.c | 2 +- arch/sparc/src/s698pm/s698pm.h | 12 ++------ .../s698pm/{s698pm_cpupause.c => s698pm_smpcall.c} | 20 +++++-------- arch/x86_64/include/intel64/irq.h | 4 +-- arch/x86_64/src/intel64/CMakeLists.txt | 2 +- arch/x86_64/src/intel64/Make.defs | 2 +- arch/x86_64/src/intel64/intel64_cpustart.c | 12 ++++---- .../{intel64_cpupause.c => intel64_smpcall.c} | 28 ++++++++---------- arch/xtensa/src/common/Make.defs | 2 +- arch/xtensa/src/common/xtensa.h | 2 +- .../common/{xtensa_cpupause.c => xtensa_smpcall.c} | 27 +++++------------- arch/xtensa/src/esp32/esp32_intercpu_interrupt.c | 4 +-- .../src/esp32s3/esp32s3_intercpu_interrupt.c | 4 +-- include/nuttx/arch.h | 28 +++++++++--------- sched/sched/sched_addreadytorun.c | 2 +- 60 files changed, 268 insertions(+), 402 deletions(-) diff --git a/arch/arm/include/cxd56xx/irq.h b/arch/arm/include/cxd56xx/irq.h index 325d2f0e6a..4269825b5d 100644 --- a/arch/arm/include/cxd56xx/irq.h +++ b/arch/arm/include/cxd56xx/irq.h @@ -158,7 +158,7 @@ #define CXD56_IRQ_SPH13 (CXD56_IRQ_EXTINT+93) /* SPH13 IRQ number */ #define CXD56_IRQ_SPH14 (CXD56_IRQ_EXTINT+94) /* SPH14 IRQ number */ #define CXD56_IRQ_SPH15 (CXD56_IRQ_EXTINT+95) /* SPH15 IRQ number */ -#define CXD56_IRQ_SW_INT (CXD56_IRQ_EXTINT+96) /* SW_INT IRQ number */ +#define CXD56_IRQ_SMP_CALL (CXD56_IRQ_EXTINT+96) /* SMP_CALL IRQ number */ #define CXD56_IRQ_TIMER0 (CXD56_IRQ_EXTINT+97) /* TIMER0 IRQ number */ #define CXD56_IRQ_TIMER1 (CXD56_IRQ_EXTINT+98) /* TIMER1 IRQ number */ #define CXD56_IRQ_TIMER2 (CXD56_IRQ_EXTINT+99) /* TIMER2 IRQ number */ diff --git a/arch/arm/include/lc823450/irq.h b/arch/arm/include/lc823450/irq.h index 72d8115aa6..56c4f96d1a 100644 --- a/arch/arm/include/lc823450/irq.h +++ b/arch/arm/include/lc823450/irq.h @@ -59,11 +59,11 @@ #define LC823450_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */ #define LC823450_IRQ_CTXM3_00 (LC823450_IRQ_INTERRUPTS+0) /* 16: CortexM3_00 interrupt */ -#define LC823450_IRQ_CTXM3_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */ +#define LC823450_IRQ_SMP_CALL_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */ #define LC823450_IRQ_CTXM3_02 (LC823450_IRQ_INTERRUPTS+2) /* 18: CortexM3_02 interrupt */ #define LC823450_IRQ_CTXM3_03 (LC823450_IRQ_INTERRUPTS+3) /* 19: CortexM3_03 interrupt */ #define LC823450_IRQ_CTXM3_10 (LC823450_IRQ_INTERRUPTS+4) /* 20: CortexM3_00 interrupt */ -#define LC823450_IRQ_CTXM3_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */ +#define LC823450_IRQ_SMP_CALL_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */ #define LC823450_IRQ_CTXM3_12 (LC823450_IRQ_INTERRUPTS+6) /* 22: CortexM3_02 interrupt */ #define LC823450_IRQ_CTXM3_13 (LC823450_IRQ_INTERRUPTS+7) /* 23: CortexM3_03 interrupt */ #define LC823450_IRQ_LPDSP0 (LC823450_IRQ_INTERRUPTS+8) /* 24: LPDSP0 interrupt */ diff --git a/arch/arm/include/rp2040/irq.h b/arch/arm/include/rp2040/irq.h index a8b776f8c6..0b79f6f078 100644 --- a/arch/arm/include/rp2040/irq.h +++ b/arch/arm/include/rp2040/irq.h @@ -75,8 +75,8 @@ #define RP2040_DMA_IRQ_1 (RP2040_IRQ_EXTINT+12) #define RP2040_IO_IRQ_BANK0 (RP2040_IRQ_EXTINT+13) #define RP2040_IO_IRQ_QSPI (RP2040_IRQ_EXTINT+14) -#define RP2040_SIO_IRQ_PROC0 (RP2040_IRQ_EXTINT+15) -#define RP2040_SIO_IRQ_PROC1 (RP2040_IRQ_EXTINT+16) +#define RP2040_SMP_CALL_PROC0 (RP2040_IRQ_EXTINT+15) +#define RP2040_SMP_CALL_PROC1 (RP2040_IRQ_EXTINT+16) #define RP2040_CLOCKS_IRQ (RP2040_IRQ_EXTINT+17) #define RP2040_SPI0_IRQ (RP2040_IRQ_EXTINT+18) #define RP2040_SPI1_IRQ (RP2040_IRQ_EXTINT+19) diff --git a/arch/arm/include/sam34/sam4cm_irq.h b/arch/arm/include/sam34/sam4cm_irq.h index 959ef7d8b7..815fc5e5fe 100644 --- a/arch/arm/include/sam34/sam4cm_irq.h +++ b/arch/arm/include/sam34/sam4cm_irq.h @@ -114,7 +114,7 @@ #define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */ #define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */ #define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ -#define SAM_IRQ_IPC0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */ +#define SAM_IRQ_SMP_CALL0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */ #define SAM_IRQ_SLCDC (SAM_IRQ_EXTINT+SAM_PID_SLCDC) /* PID 32: Segment LCD Controller */ #define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* PID 33: True Random Generator */ #define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* PID 34: Integrity Check Module */ @@ -122,7 +122,7 @@ #define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* PID 36: Advanced Enhanced Standard */ #define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 37: Parallel I/O Controller C */ #define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 38: Universal Asynchronous Receiver Transmitter 1 */ -#define SAM_IRQ_IPC1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */ +#define SAM_IRQ_SMP_CALL1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */ #define SAM_IRQ_RESERVED_40 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */ #define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 41: Pulse Width Modulation */ #define SAM_IRQ_SRAM (SAM_IRQ_EXTINT+SAM_PID_SRAM) /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */ diff --git a/arch/arm/src/armv7-a/CMakeLists.txt b/arch/arm/src/armv7-a/CMakeLists.txt index 042be6cffb..3fcc9a3679 100644 --- a/arch/arm/src/armv7-a/CMakeLists.txt +++ b/arch/arm/src/armv7-a/CMakeLists.txt @@ -109,7 +109,7 @@ if(CONFIG_ARCH_FPU) endif() if(CONFIG_SMP) - list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c) + list(APPEND SRCS arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c arm_scu.c) endif() if(CONFIG_ARCH_HAVE_PSCI) diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs index f757e3d11c..8aa01008f3 100644 --- a/arch/arm/src/armv7-a/Make.defs +++ b/arch/arm/src/armv7-a/Make.defs @@ -94,7 +94,7 @@ ifeq ($(CONFIG_ARCH_FPU),y) endif ifeq ($(CONFIG_SMP),y) - CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c + CMN_CSRCS += arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c CMN_CSRCS += arm_scu.c endif diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 78f189e2c9..66d9f3547f 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -219,9 +219,8 @@ void arm_gic0_initialize(void) /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC, - arm_pause_async_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL)); #endif arm_gic_dump("Exit arm_gic0_initialize", true, 0); @@ -754,27 +753,6 @@ void arm_cpu_sgi(int sgi, unsigned int cpuset) putreg32(regval, GIC_ICDSGIR); } -#ifdef CONFIG_SMP -/**************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu. - * - * Input Parameters: - * cpuset - The set of CPUs to receive the SGI. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset) -{ - up_trigger_irq(GIC_SMP_CPUCALL, cpuset); -} -#endif - /**************************************************************************** * Name: up_get_legacy_irq * diff --git a/arch/arm/src/armv7-r/arm_cpupause.c b/arch/arm/src/armv7-a/arm_smpcall.c similarity index 80% rename from arch/arm/src/armv7-r/arm_cpupause.c rename to arch/arm/src/armv7-a/arm_smpcall.c index 51a9af8dc0..29f5ecbcc3 100644 --- a/arch/arm/src/armv7-r/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-r/arm_cpupause.c + * arch/arm/src/armv7-a/arm_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -47,10 +47,10 @@ ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_async_handler + * Name: arm_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -66,7 +66,7 @@ * ****************************************************************************/ -int arm_pause_async_handler(int irq, void *context, void *arg) +int arm_smp_sched_handler(int irq, void *context, void *arg) { int cpu = this_cpu(); @@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { - arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu)); + arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu)); return OK; } +/**************************************************************************** + * Name: up_send_smp_call + * + * Description: + * Send smp call to target cpu. + * + * Input Parameters: + * cpuset - The set of CPUs to receive the SGI. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_send_smp_call(cpu_set_t cpuset) +{ + up_trigger_irq(GIC_SMP_CALL, cpuset); +} + #endif /* CONFIG_SMP */ diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h index 34d53db92c..48769ee644 100644 --- a/arch/arm/src/armv7-a/gic.h +++ b/arch/arm/src/armv7-a/gic.h @@ -635,14 +635,12 @@ #ifdef CONFIG_ARCH_TRUSTZONE_SECURE # define GIC_SMP_CPUSTART GIC_IRQ_SGI9 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI11 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12 +# define GIC_SMP_CALL GIC_IRQ_SGI10 +# define GIC_SMP_SCHED GIC_IRQ_SGI11 #else # define GIC_SMP_CPUSTART GIC_IRQ_SGI1 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI3 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4 +# define GIC_SMP_CALL GIC_IRQ_SGI2 +# define GIC_SMP_SCHED GIC_IRQ_SGI3 #endif /**************************************************************************** @@ -836,10 +834,10 @@ int arm_start_handler(int irq, void *context, void *arg); #endif /**************************************************************************** - * Name: arm_pause_async_handler + * Name: arm_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -856,7 +854,7 @@ int arm_start_handler(int irq, void *context, void *arg); ****************************************************************************/ #ifdef CONFIG_SMP -int arm_pause_async_handler(int irq, void *context, void *arg); +int arm_smp_sched_handler(int irq, void *context, void *arg); #endif /**************************************************************************** * Name: arm_gic_dump diff --git a/arch/arm/src/armv7-r/CMakeLists.txt b/arch/arm/src/armv7-r/CMakeLists.txt index 784b9ab094..0fbbeb6882 100644 --- a/arch/arm/src/armv7-r/CMakeLists.txt +++ b/arch/arm/src/armv7-r/CMakeLists.txt @@ -71,7 +71,7 @@ if(CONFIG_SMP) SRCS arm_cpuhead.S arm_cpustart.c - arm_cpupause.c + arm_smpcall.c arm_cpuidlestack.c arm_scu.c) endif() diff --git a/arch/arm/src/armv7-r/Make.defs b/arch/arm/src/armv7-r/Make.defs index 8cf8645ba2..bc33650802 100644 --- a/arch/arm/src/armv7-r/Make.defs +++ b/arch/arm/src/armv7-r/Make.defs @@ -59,6 +59,6 @@ endif ifeq ($(CONFIG_SMP),y) CMN_ASRCS += arm_cpuhead.S - CMN_CSRCS += arm_cpustart.c arm_cpupause.c + CMN_CSRCS += arm_cpustart.c arm_smpcall.c CMN_CSRCS += arm_cpuidlestack.c arm_scu.c endif diff --git a/arch/arm/src/armv7-r/arm_gicv2.c b/arch/arm/src/armv7-r/arm_gicv2.c index 7851e6fcd7..4ddf85d04a 100644 --- a/arch/arm/src/armv7-r/arm_gicv2.c +++ b/arch/arm/src/armv7-r/arm_gicv2.c @@ -160,9 +160,8 @@ void arm_gic0_initialize(void) /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC, - arm_pause_async_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL)); #endif arm_gic_dump("Exit arm_gic0_initialize", true, 0); @@ -659,24 +658,4 @@ int arm_gic_irq_trigger(int irq, bool edge) return -EINVAL; } -# ifdef CONFIG_SMP -/**************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu. - * - * Input Parameters: - * cpuset - The set of CPUs to receive the SGI. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset) -{ - up_trigger_irq(GIC_SMP_CPUCALL, cpuset); -} -# endif #endif /* CONFIG_ARMV7R_HAVE_GICv2 */ diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-r/arm_smpcall.c similarity index 80% rename from arch/arm/src/armv7-a/arm_cpupause.c rename to arch/arm/src/armv7-r/arm_smpcall.c index 271ead55b7..524e374005 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-r/arm_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/armv7-a/arm_cpupause.c + * arch/arm/src/armv7-r/arm_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -47,10 +47,10 @@ ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_async_handler + * Name: arm_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -66,7 +66,7 @@ * ****************************************************************************/ -int arm_pause_async_handler(int irq, void *context, void *arg) +int arm_smp_sched_handler(int irq, void *context, void *arg) { int cpu = this_cpu(); @@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { - arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu)); + arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu)); return OK; } +/**************************************************************************** + * Name: up_send_smp_call + * + * Description: + * Send smp call to target cpu. + * + * Input Parameters: + * cpuset - The set of CPUs to receive the SGI. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_send_smp_call(cpu_set_t cpuset) +{ + up_trigger_irq(GIC_SMP_CALL, cpuset); +} + #endif /* CONFIG_SMP */ diff --git a/arch/arm/src/armv7-r/gic.h b/arch/arm/src/armv7-r/gic.h index 5a0a284e52..eef4e3cb90 100644 --- a/arch/arm/src/armv7-r/gic.h +++ b/arch/arm/src/armv7-r/gic.h @@ -608,14 +608,12 @@ #ifdef CONFIG_ARCH_TRUSTZONE_SECURE # define GIC_SMP_CPUSTART GIC_IRQ_SGI9 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI11 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12 +# define GIC_SMP_CALL GIC_IRQ_SGI10 +# define GIC_SMP_SCHED GIC_IRQ_SGI11 #else # define GIC_SMP_CPUSTART GIC_IRQ_SGI1 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI3 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4 +# define GIC_SMP_CALL GIC_IRQ_SGI2 +# define GIC_SMP_SCHED GIC_IRQ_SGI3 #endif /**************************************************************************** @@ -806,10 +804,10 @@ int arm_start_handler(int irq, void *context, void *arg); #endif /**************************************************************************** - * Name: arm_pause_async_handler + * Name: arm_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -826,7 +824,7 @@ int arm_start_handler(int irq, void *context, void *arg); ****************************************************************************/ #ifdef CONFIG_SMP -int arm_pause_async_handler(int irq, void *context, void *arg); +int arm_smp_sched_handler(int irq, void *context, void *arg); #endif /**************************************************************************** diff --git a/arch/arm/src/armv8-r/arm_gic.h b/arch/arm/src/armv8-r/arm_gic.h index b8b9b588d9..44057a4378 100644 --- a/arch/arm/src/armv8-r/arm_gic.h +++ b/arch/arm/src/armv8-r/arm_gic.h @@ -311,14 +311,12 @@ #ifdef CONFIG_ARCH_TRUSTZONE_SECURE # define GIC_SMP_CPUSTART GIC_IRQ_SGI9 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI11 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12 +# define GIC_SMP_CALL GIC_IRQ_SGI10 +# define GIC_SMP_SCHED GIC_IRQ_SGI11 #else # define GIC_SMP_CPUSTART GIC_IRQ_SGI1 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI3 -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4 +# define GIC_SMP_CALL GIC_IRQ_SGI2 +# define GIC_SMP_SCHED GIC_IRQ_SGI3 #endif /**************************************************************************** @@ -335,7 +333,7 @@ int arm_gic_raise_sgi(unsigned int sgi_id, uint16_t target_list); #ifdef CONFIG_SMP -int arm_pause_async_handler(int irq, void *context, void *arg); +int arm_smp_sched_handler(int irq, void *context, void *arg); void arm_gic_secondary_init(void); #endif diff --git a/arch/arm/src/armv8-r/arm_gicv3.c b/arch/arm/src/armv8-r/arm_gicv3.c index d7dfe2b47f..15aac99960 100644 --- a/arch/arm/src/armv8-r/arm_gicv3.c +++ b/arch/arm/src/armv8-r/arm_gicv3.c @@ -567,10 +567,8 @@ static void gicv3_dist_init(void) #ifdef CONFIG_SMP /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ - DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC, - arm64_pause_async_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, - nxsched_smp_call_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL)); #endif } @@ -814,8 +812,8 @@ static void arm_gic_init(void) gicv3_cpuif_init(); #ifdef CONFIG_SMP - up_enable_irq(GIC_SMP_CPUCALL); - up_enable_irq(GIC_SMP_CPUPAUSE_ASYNC); + up_enable_irq(GIC_SMP_CALL); + up_enable_irq(GIC_SMP_SCHED); #endif } @@ -843,24 +841,4 @@ void arm_gic_secondary_init(void) arm_gic_init(); } -# ifdef CONFIG_SMP -/*************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu. - * - * Input Parameters: - * cpuset - The set of CPUs to receive the SGI. - * - * Returned Value: - * None. - * - ***************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset) -{ - up_trigger_irq(GIC_SMP_CPUCALL, cpuset); -} -# endif #endif diff --git a/arch/arm/src/cxd56xx/CMakeLists.txt b/arch/arm/src/cxd56xx/CMakeLists.txt index a19a29a15d..cb7315f33b 100644 --- a/arch/arm/src/cxd56xx/CMakeLists.txt +++ b/arch/arm/src/cxd56xx/CMakeLists.txt @@ -42,7 +42,7 @@ set(SRCS if(CONFIG_SMP) list(APPEND SRCS cxd56_cpuidlestack.c) list(APPEND SRCS cxd56_cpuindex.c) - list(APPEND SRCS cxd56_cpupause.c) + list(APPEND SRCS cxd56_smpcall.c) list(APPEND SRCS cxd56_cpustart.c) if(CONFIG_CXD56_TESTSET) list(APPEND SRCS cxd56_testset.c) diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index 54c653c050..ece4ac2b54 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -41,7 +41,7 @@ CHIP_CSRCS += cxd56_sysctl.c ifeq ($(CONFIG_SMP), y) CHIP_CSRCS += cxd56_cpuidlestack.c CHIP_CSRCS += cxd56_cpuindex.c -CHIP_CSRCS += cxd56_cpupause.c +CHIP_CSRCS += cxd56_smpcall.c CHIP_CSRCS += cxd56_cpustart.c ifeq ($(CONFIG_CXD56_TESTSET),y) CHIP_CSRCS += cxd56_testset.c diff --git a/arch/arm/src/cxd56xx/cxd56_cpustart.c b/arch/arm/src/cxd56xx/cxd56_cpustart.c index dcac15f589..be32c9e530 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpustart.c +++ b/arch/arm/src/cxd56xx/cxd56_cpustart.c @@ -72,7 +72,7 @@ volatile static spinlock_t g_appdsp_boot; -extern int arm_pause_handler(int irq, void *c, void *arg); +extern int cxd56_smp_call_handler(int irq, void *c, void *arg); /**************************************************************************** * Private Functions @@ -117,8 +117,8 @@ static void appdsp_boot(void) /* Enable SW_INT */ - irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL); - up_enable_irq(CXD56_IRQ_SW_INT); + irq_attach(CXD56_IRQ_SMP_CALL, cxd56_smp_call_handler, NULL); + up_enable_irq(CXD56_IRQ_SMP_CALL); spin_unlock(&g_appdsp_boot); @@ -232,8 +232,8 @@ int up_cpu_start(int cpu) /* Setup SW_INT for this APP_DSP0 */ - irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL); - up_enable_irq(CXD56_IRQ_SW_INT); + irq_attach(CXD56_IRQ_SMP_CALL, cxd56_smp_call_handler, NULL); + up_enable_irq(CXD56_IRQ_SMP_CALL); } spin_lock(&g_appdsp_boot); diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 1bc9ba49d5..d9d24ad496 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -470,7 +470,7 @@ void up_enable_irq(int irq) /* EXTINT needs to be handled on CPU0 to avoid deadlock */ - if (irq > CXD56_IRQ_EXTINT && irq != CXD56_IRQ_SW_INT && 0 != cpu) + if (irq > CXD56_IRQ_EXTINT && irq != CXD56_IRQ_SMP_CALL && 0 != cpu) { up_send_irqreq(0, irq, 0); return; diff --git a/arch/arm/src/cxd56xx/cxd56_cpupause.c b/arch/arm/src/cxd56xx/cxd56_smpcall.c similarity index 94% rename from arch/arm/src/cxd56xx/cxd56_cpupause.c rename to arch/arm/src/cxd56xx/cxd56_smpcall.c index fe655bff7f..360e83ad2f 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpupause.c +++ b/arch/arm/src/cxd56xx/cxd56_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/cxd56xx/cxd56_cpupause.c + * arch/arm/src/cxd56xx/cxd56_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -118,20 +118,14 @@ static bool handle_irqreq(int cpu) ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_handler + * Name: cxd56_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int arm_pause_handler(int irq, void *c, void *arg) +int cxd56_smp_call_handler(int irq, void *c, void *arg) { int cpu = this_cpu(); int ret = OK; @@ -152,7 +146,7 @@ int arm_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -170,7 +164,7 @@ int arm_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Generate IRQ for CPU(cpu) */ @@ -200,7 +194,7 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } } diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs index 905f3a1786..4b3bf6ca42 100644 --- a/arch/arm/src/lc823450/Make.defs +++ b/arch/arm/src/lc823450/Make.defs @@ -92,7 +92,7 @@ endif ifeq ($(CONFIG_SMP), y) CHIP_CSRCS += lc823450_cpuidlestack.c CHIP_CSRCS += lc823450_cpuindex.c -CHIP_CSRCS += lc823450_cpupause.c +CHIP_CSRCS += lc823450_smpcall.c CHIP_CSRCS += lc823450_cpustart.c CHIP_CSRCS += lc823450_testset.c CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS)) diff --git a/arch/arm/src/lc823450/lc823450_cpustart.c b/arch/arm/src/lc823450/lc823450_cpustart.c index 34936eee19..26d1d8cbc2 100644 --- a/arch/arm/src/lc823450/lc823450_cpustart.c +++ b/arch/arm/src/lc823450/lc823450_cpustart.c @@ -69,7 +69,7 @@ static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; * Private Functions ****************************************************************************/ -extern int lc823450_pause_handler(int irq, void *c, void *arg); +extern int lc823450_smp_call_handler(int irq, void *c, void *arg); /**************************************************************************** * Name: cpu1_boot @@ -106,8 +106,8 @@ static void cpu1_boot(void) up_enable_irq(LC823450_IRQ_MEMFAULT); #endif - irq_attach(LC823450_IRQ_CTXM3_01, lc823450_pause_handler, NULL); - up_enable_irq(LC823450_IRQ_CTXM3_01); + irq_attach(LC823450_IRQ_SMP_CALL_01, lc823450_smp_call_handler, NULL); + up_enable_irq(LC823450_IRQ_SMP_CALL_01); } spin_unlock(&g_cpu_wait[0]); @@ -193,8 +193,8 @@ int up_cpu_start(int cpu) /* IRQ setup CPU1->CPU0 */ - irq_attach(LC823450_IRQ_CTXM3_11, lc823450_pause_handler, NULL); - up_enable_irq(LC823450_IRQ_CTXM3_11); + irq_attach(LC823450_IRQ_SMP_CALL_11, lc823450_smp_call_handler, NULL); + up_enable_irq(LC823450_IRQ_SMP_CALL_11); spin_lock(&g_cpu_wait[0]); diff --git a/arch/arm/src/lc823450/lc823450_cpupause.c b/arch/arm/src/lc823450/lc823450_smpcall.c similarity index 89% rename from arch/arm/src/lc823450/lc823450_cpupause.c rename to arch/arm/src/lc823450/lc823450_smpcall.c index 162e79da8b..8aa5bce3f8 100644 --- a/arch/arm/src/lc823450/lc823450_cpupause.c +++ b/arch/arm/src/lc823450/lc823450_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/lc823450/lc823450_cpupause.c + * arch/arm/src/lc823450/lc823450_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -57,20 +57,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: lc823450_pause_handler + * Name: lc823450_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int lc823450_pause_handler(int irq, void *c, void *arg) +int lc823450_smp_call_handler(int irq, void *c, void *arg) { int cpu = this_cpu(); @@ -78,7 +72,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg) /* Clear : Pause IRQ */ - if (irq == LC823450_IRQ_CTXM3_01) + if (irq == LC823450_IRQ_SMP_CALL_01) { DPRINTF("CPU0 -> CPU1\n"); putreg32(IPICLR_INTISR0_CLR_1, IPICLR); @@ -95,7 +89,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -113,7 +107,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Execute Pause IRQ to CPU(cpu) */ @@ -150,6 +144,6 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } } diff --git a/arch/arm/src/rp2040/Make.defs b/arch/arm/src/rp2040/Make.defs index 76aab70927..1fbf4b4cd0 100644 --- a/arch/arm/src/rp2040/Make.defs +++ b/arch/arm/src/rp2040/Make.defs @@ -37,7 +37,7 @@ CHIP_CSRCS += rp2040_pll.c ifeq ($(CONFIG_SMP),y) CHIP_CSRCS += rp2040_cpuindex.c CHIP_CSRCS += rp2040_cpustart.c -CHIP_CSRCS += rp2040_cpupause.c +CHIP_CSRCS += rp2040_smpcall.c CHIP_CSRCS += rp2040_cpuidlestack.c CHIP_CSRCS += rp2040_testset.c CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS)) diff --git a/arch/arm/src/rp2040/rp2040_cpustart.c b/arch/arm/src/rp2040/rp2040_cpustart.c index 230246497e..18893edfd8 100644 --- a/arch/arm/src/rp2040/rp2040_cpustart.c +++ b/arch/arm/src/rp2040/rp2040_cpustart.c @@ -67,7 +67,7 @@ volatile static spinlock_t g_core1_boot; -extern int arm_pause_handler(int irq, void *c, void *arg); +extern int rp2040_smp_call_handler(int irq, void *c, void *arg); /**************************************************************************** * Private Functions @@ -151,8 +151,8 @@ static void core1_boot(void) /* Enable inter-processor FIFO interrupt */ - irq_attach(RP2040_SIO_IRQ_PROC1, arm_pause_handler, NULL); - up_enable_irq(RP2040_SIO_IRQ_PROC1); + irq_attach(RP2040_SMP_CALL_PROC1, rp2040_smp_call_handler, NULL); + up_enable_irq(RP2040_SMP_CALL_PROC1); spin_unlock(&g_core1_boot); @@ -247,8 +247,8 @@ int up_cpu_start(int cpu) /* Enable inter-processor FIFO interrupt */ - irq_attach(RP2040_SIO_IRQ_PROC0, arm_pause_handler, NULL); - up_enable_irq(RP2040_SIO_IRQ_PROC0); + irq_attach(RP2040_SMP_CALL_PROC0, rp2040_smp_call_handler, NULL); + up_enable_irq(RP2040_SMP_CALL_PROC0); spin_lock(&g_core1_boot); diff --git a/arch/arm/src/rp2040/rp2040_irq.c b/arch/arm/src/rp2040/rp2040_irq.c index 4791a5bb1b..8317f52b4d 100644 --- a/arch/arm/src/rp2040/rp2040_irq.c +++ b/arch/arm/src/rp2040/rp2040_irq.c @@ -276,7 +276,7 @@ void up_disable_irq(int irq) DEBUGASSERT((unsigned)irq < NR_IRQS); #ifdef CONFIG_SMP - if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 && + if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SMP_CALL_PROC1 && this_cpu() != 0) { /* Must be handled by Core 0 */ @@ -324,7 +324,7 @@ void up_enable_irq(int irq) DEBUGASSERT((unsigned)irq < NR_IRQS); #ifdef CONFIG_SMP - if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 && + if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SMP_CALL_PROC1 && this_cpu() != 0) { /* Must be handled by Core 0 */ diff --git a/arch/arm/src/rp2040/rp2040_cpupause.c b/arch/arm/src/rp2040/rp2040_smpcall.c similarity index 93% rename from arch/arm/src/rp2040/rp2040_cpupause.c rename to arch/arm/src/rp2040/rp2040_smpcall.c index 434bdd4fef..ff889320f9 100644 --- a/arch/arm/src/rp2040/rp2040_cpupause.c +++ b/arch/arm/src/rp2040/rp2040_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/rp2040/rp2040_cpupause.c + * arch/arm/src/rp2040/rp2040_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -81,20 +81,14 @@ static void rp2040_handle_irqreq(int irqreq) ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_handler + * Name: rp2040_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int arm_pause_handler(int irq, void *c, void *arg) +int rp2040_smp_call_handler(int irq, void *c, void *arg) { int cpu = this_cpu(); int irqreq; @@ -135,7 +129,7 @@ int arm_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -153,7 +147,7 @@ int arm_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Generate IRQ for CPU(cpu) */ @@ -185,7 +179,7 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } } diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index faad35b62f..ca7bfb75ed 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -138,7 +138,7 @@ endif # CONFIG_SAM34_TC ifeq ($(CONFIG_SMP),y) CHIP_CSRCS += sam4cm_cpuindex.c sam4cm_cpuidlestack.c -CHIP_CSRCS += sam4cm_cpupause.c sam4cm_cpustart.c +CHIP_CSRCS += sam4cm_smpcall.c sam4cm_cpustart.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += sam4cm_idle.c endif diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c index 4e0ffc3020..70357960c1 100644 --- a/arch/arm/src/sam34/sam4cm_cpustart.c +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -64,7 +64,7 @@ ****************************************************************************/ volatile static spinlock_t g_cpu1_boot; -extern int arm_pause_handler(int irq, void *c, void *arg); +extern int sam4cm_smp_call_handler(int irq, void *c, void *arg); /**************************************************************************** * Public Functions @@ -108,8 +108,8 @@ static void cpu1_boot(void) /* Enable : write-only */ putreg32(0x1, SAM_IPC1_IECR); - irq_attach(SAM_IRQ_IPC1, arm_pause_handler, NULL); - up_enable_irq(SAM_IRQ_IPC1); + irq_attach(SAM_IRQ_SMP_CALL1, sam4cm_smp_call_handler, NULL); + up_enable_irq(SAM_IRQ_SMP_CALL1); } spin_unlock(&g_cpu1_boot); @@ -218,8 +218,8 @@ int up_cpu_start(int cpu) sam_ipc0_enableclk(); putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */ putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */ - irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL); - up_enable_irq(SAM_IRQ_IPC0); + irq_attach(SAM_IRQ_SMP_CALL0, sam4cm_smp_call_handler, NULL); + up_enable_irq(SAM_IRQ_SMP_CALL0); spin_lock(&g_cpu1_boot); diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_smpcall.c similarity index 91% rename from arch/arm/src/sam34/sam4cm_cpupause.c rename to arch/arm/src/sam34/sam4cm_smpcall.c index aba110580a..ff92026230 100644 --- a/arch/arm/src/sam34/sam4cm_cpupause.c +++ b/arch/arm/src/sam34/sam4cm_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/sam34/sam4cm_cpupause.c + * arch/arm/src/sam34/sam4cm_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -59,20 +59,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_handler + * Name: sam4cm_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int arm_pause_handler(int irq, void *c, void *arg) +int sam4cm_smp_call_handler(int irq, void *c, void *arg) { int cpu = this_cpu(); @@ -99,7 +93,7 @@ int arm_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -117,7 +111,7 @@ int arm_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Execute Pause IRQ to CPU(cpu) */ @@ -156,7 +150,7 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } } diff --git a/arch/arm64/src/common/CMakeLists.txt b/arch/arm64/src/common/CMakeLists.txt index 6f8877a37a..03da77a59d 100644 --- a/arch/arm64/src/common/CMakeLists.txt +++ b/arch/arm64/src/common/CMakeLists.txt @@ -71,7 +71,7 @@ endif() if(CONFIG_SMP) list(APPEND SRCS arm64_cpuidlestack.c arm64_cpustart.c) - list(APPEND SRCS arm64_cpupause.c) + list(APPEND SRCS arm64_smpcall.c) endif() if(CONFIG_BUILD_KERNEL) diff --git a/arch/arm64/src/common/Make.defs b/arch/arm64/src/common/Make.defs index 0c9bf06db0..4a0470f0cb 100644 --- a/arch/arm64/src/common/Make.defs +++ b/arch/arm64/src/common/Make.defs @@ -84,7 +84,7 @@ endif ifeq ($(CONFIG_SMP),y) CMN_CSRCS += arm64_cpuidlestack.c arm64_cpustart.c -CMN_CSRCS += arm64_cpupause.c +CMN_CSRCS += arm64_smpcall.c endif ifeq ($(CONFIG_BUILD_KERNEL),y) diff --git a/arch/arm64/src/common/arm64_gic.h b/arch/arm64/src/common/arm64_gic.h index 20ae8d8e57..ce31277205 100644 --- a/arch/arm64/src/common/arm64_gic.h +++ b/arch/arm64/src/common/arm64_gic.h @@ -281,15 +281,13 @@ #define GIC_IRQ_SGI15 15 #ifdef CONFIG_ARCH_TRUSTZONE_SECURE -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI8 -# define GIC_SMP_CPUSTART GIC_IRQ_SGI9 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI11 +# define GIC_SMP_SCHED GIC_IRQ_SGI9 +# define GIC_SMP_CPUSTART GIC_IRQ_SGI10 +# define GIC_SMP_CALL GIC_IRQ_SGI11 #else -# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI0 -# define GIC_SMP_CPUSTART GIC_IRQ_SGI1 -# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2 -# define GIC_SMP_CPUCALL GIC_IRQ_SGI3 +# define GIC_SMP_SCHED GIC_IRQ_SGI1 +# define GIC_SMP_CPUSTART GIC_IRQ_SGI2 +# define GIC_SMP_CALL GIC_IRQ_SGI3 #endif /**************************************************************************** @@ -329,10 +327,10 @@ int arm64_gic_v2m_initialize(void); #ifdef CONFIG_SMP /**************************************************************************** - * Name: arm64_pause_async_handler + * Name: arm64_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -348,7 +346,7 @@ int arm64_gic_v2m_initialize(void); * ****************************************************************************/ -int arm64_pause_async_handler(int irq, void *context, void *arg); +int arm64_smp_sched_handler(int irq, void *context, void *arg); void arm64_gic_secondary_init(void); diff --git a/arch/arm64/src/common/arm64_gicv2.c b/arch/arm64/src/common/arm64_gicv2.c index bdeccde1ee..06d85292b7 100644 --- a/arch/arm64/src/common/arm64_gicv2.c +++ b/arch/arm64/src/common/arm64_gicv2.c @@ -864,10 +864,8 @@ static void arm_gic0_initialize(void) #ifdef CONFIG_SMP /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ - DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC, - arm64_pause_async_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, - nxsched_smp_call_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL)); #endif } @@ -1489,26 +1487,6 @@ void arm64_gic_raise_sgi(unsigned int sgi, uint16_t cpuset) arm_cpu_sgi(sgi, cpuset); } -# ifdef CONFIG_SMP -/**************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu. - * - * Input Parameters: - * cpuset - The set of CPUs to receive the SGI. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset) -{ - up_trigger_irq(GIC_SMP_CPUCALL, cpuset); -} -# endif #endif /* CONFIG_SMP */ /**************************************************************************** diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c index d501a76786..aad758376c 100644 --- a/arch/arm64/src/common/arm64_gicv3.c +++ b/arch/arm64/src/common/arm64_gicv3.c @@ -653,10 +653,8 @@ static void gicv3_dist_init(void) #ifdef CONFIG_SMP /* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */ - DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC, - arm64_pause_async_handler, NULL)); - DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, - nxsched_smp_call_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL)); + DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL)); #endif } @@ -952,8 +950,8 @@ static void arm64_gic_init(void) gicv3_cpuif_init(); #ifdef CONFIG_SMP - up_enable_irq(GIC_SMP_CPUPAUSE_ASYNC); - up_enable_irq(GIC_SMP_CPUCALL); + up_enable_irq(GIC_SMP_SCHED); + up_enable_irq(GIC_SMP_CALL); #endif } @@ -980,27 +978,6 @@ void arm64_gic_secondary_init(void) { arm64_gic_init(); } - -# ifdef CONFIG_SMP -/*************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu. - * - * Input Parameters: - * cpuset - The set of CPUs to receive the SGI. - * - * Returned Value: - * None. - * - ***************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset) -{ - up_trigger_irq(GIC_SMP_CPUCALL, cpuset); -} -# endif #endif /*************************************************************************** diff --git a/arch/arm64/src/common/arm64_cpupause.c b/arch/arm64/src/common/arm64_smpcall.c similarity index 80% rename from arch/arm64/src/common/arm64_cpupause.c rename to arch/arm64/src/common/arm64_smpcall.c index 4c893bfad0..e1672bd21b 100644 --- a/arch/arm64/src/common/arm64_cpupause.c +++ b/arch/arm64/src/common/arm64_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm64/src/common/arm64_cpupause.c + * arch/arm64/src/common/arm64_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -46,10 +46,10 @@ ****************************************************************************/ /**************************************************************************** - * Name: arm64_pause_async_handler + * Name: arm64_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for sched. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -65,7 +65,7 @@ * ****************************************************************************/ -int arm64_pause_async_handler(int irq, void *context, void *arg) +int arm64_smp_sched_handler(int irq, void *context, void *arg) { int cpu = this_cpu(); @@ -75,7 +75,7 @@ int arm64_pause_async_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -93,11 +93,30 @@ int arm64_pause_async_handler(int irq, void *context, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Execute SGI2 */ - arm64_gic_raise_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu)); + arm64_gic_raise_sgi(GIC_SMP_SCHED, (1 << cpu)); return OK; } + +/**************************************************************************** + * Name: up_send_smp_call + * + * Description: + * Send smp call to target cpu. + * + * Input Parameters: + * cpuset - The set of CPUs to receive the SGI. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_send_smp_call(cpu_set_t cpuset) +{ + up_trigger_irq(GIC_SMP_CALL, cpuset); +} diff --git a/arch/risc-v/src/common/CMakeLists.txt b/arch/risc-v/src/common/CMakeLists.txt index 1a41dc1f30..9340255205 100644 --- a/arch/risc-v/src/common/CMakeLists.txt +++ b/arch/risc-v/src/common/CMakeLists.txt @@ -41,7 +41,7 @@ if(NOT CONFIG_ALARM_ARCH) endif() if(CONFIG_SMP) - list(APPEND SRCS riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c) + list(APPEND SRCS riscv_cpuindex.c riscv_smpcall.c riscv_cpustart.c) endif() if(CONFIG_RISCV_MISALIGNED_HANDLER) diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs index 61cae3bbcb..4a66e52682 100644 --- a/arch/risc-v/src/common/Make.defs +++ b/arch/risc-v/src/common/Make.defs @@ -43,7 +43,7 @@ ifneq ($(CONFIG_ALARM_ARCH),y) endif ifeq ($(CONFIG_SMP),y) -CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c +CMN_CSRCS += riscv_cpuindex.c riscv_smpcall.c riscv_cpustart.c endif ifeq ($(CONFIG_RISCV_MISALIGNED_HANDLER),y) diff --git a/arch/risc-v/src/common/riscv_exception.c b/arch/risc-v/src/common/riscv_exception.c index e77a3c8ee8..1995f12ada 100644 --- a/arch/risc-v/src/common/riscv_exception.c +++ b/arch/risc-v/src/common/riscv_exception.c @@ -301,7 +301,7 @@ void riscv_exception_attach(void) irq_attach(RISCV_IRQ_RESERVED14, riscv_exception, NULL); #ifdef CONFIG_SMP - irq_attach(RISCV_IRQ_SOFT, riscv_pause_handler, NULL); + irq_attach(RISCV_IRQ_SOFT, riscv_smp_call_handler, NULL); #else irq_attach(RISCV_IRQ_SOFT, riscv_exception, NULL); #endif diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index d9165356a9..6e69c9550b 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -412,7 +412,7 @@ void riscv_stack_color(void *stackbase, size_t nbytes); #ifdef CONFIG_SMP void riscv_cpu_boot(int cpu); -int riscv_pause_handler(int irq, void *c, void *arg); +int riscv_smp_call_handler(int irq, void *c, void *arg); #endif /**************************************************************************** diff --git a/arch/risc-v/src/common/riscv_cpupause.c b/arch/risc-v/src/common/riscv_smpcall.c similarity index 89% rename from arch/risc-v/src/common/riscv_cpupause.c rename to arch/risc-v/src/common/riscv_smpcall.c index 87f0be026d..46b5f17bda 100644 --- a/arch/risc-v/src/common/riscv_cpupause.c +++ b/arch/risc-v/src/common/riscv_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/common/riscv_cpupause.c + * arch/risc-v/src/common/riscv_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -48,20 +48,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: riscv_pause_handler + * Name: riscv_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int riscv_pause_handler(int irq, void *c, void *arg) +int riscv_smp_call_handler(int irq, void *c, void *arg) { struct tcb_s *tcb; int cpu = this_cpu(); @@ -82,7 +76,7 @@ int riscv_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -100,7 +94,7 @@ int riscv_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Execute Pause IRQ to CPU(cpu) */ @@ -130,7 +124,6 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - riscv_ipi_send(cpu); + up_send_smp_sched(cpu); } } - diff --git a/arch/risc-v/src/jh7110/jh7110_timerisr.c b/arch/risc-v/src/jh7110/jh7110_timerisr.c index 920361fff6..8277ffcc4b 100644 --- a/arch/risc-v/src/jh7110/jh7110_timerisr.c +++ b/arch/risc-v/src/jh7110/jh7110_timerisr.c @@ -79,7 +79,7 @@ static int jh7110_ssoft_interrupt(int irq, void *context, void *arg) { /* We assume IPI has been issued */ - riscv_pause_handler(irq, context, arg); + riscv_smp_call_handler(irq, context, arg); } #endif diff --git a/arch/sim/src/sim/sim_smpsignal.c b/arch/sim/src/sim/sim_smpsignal.c index 6ca2953fcf..f535767aa8 100644 --- a/arch/sim/src/sim/sim_smpsignal.c +++ b/arch/sim/src/sim/sim_smpsignal.c @@ -60,23 +60,14 @@ static int sim_smp_call_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: sim_cpupause_handler + * Name: sim_smp_sched_handler * * Description: - * This is the SIGUSR signal handler. It implements the core logic of - * up_cpu_pause() on the thread of execution the simulated CPU. - * - * Input Parameters: - * irq - the interrupt number - * context - not used - * arg - not used - * - * Returned Value: - * In case of success OK (0) is returned otherwise a negative value. + * This is the handler for smp. * ****************************************************************************/ -static int sim_cpupause_handler(int irq, void *context, void *arg) +static int sim_smp_sched_handler(int irq, void *context, void *arg) { struct tcb_s *tcb; int cpu = this_cpu(); @@ -173,11 +164,11 @@ int up_cpu_start(int cpu) int sim_init_ipi(int irq) { up_enable_irq(irq); - return irq_attach(irq, sim_cpupause_handler, NULL); + return irq_attach(irq, sim_smp_sched_handler, NULL); } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -195,7 +186,7 @@ int sim_init_ipi(int irq) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Generate IRQ for CPU(cpu) */ diff --git a/arch/sparc/src/s698pm/Make.defs b/arch/sparc/src/s698pm/Make.defs index c3ce0323c8..ff1935e7ad 100644 --- a/arch/sparc/src/s698pm/Make.defs +++ b/arch/sparc/src/s698pm/Make.defs @@ -54,5 +54,5 @@ endif # Configuration-dependent files ifeq ($(CONFIG_SMP),y) -CHIP_CSRCS += s698pm_cpuindex.c s698pm_cpustart.c s698pm_cpupause.c s698pm_cpuidlestack.c +CHIP_CSRCS += s698pm_cpuindex.c s698pm_cpustart.c s698pm_smpcall.c s698pm_cpuidlestack.c endif diff --git a/arch/sparc/src/s698pm/s698pm-irq.c b/arch/sparc/src/s698pm/s698pm-irq.c index bc2fc173ec..de7f004859 100644 --- a/arch/sparc/src/s698pm/s698pm-irq.c +++ b/arch/sparc/src/s698pm/s698pm-irq.c @@ -185,7 +185,7 @@ int s698pm_cpuint_initialize(void) #if defined CONFIG_SMP /* Attach IPI interrupts */ - irq_attach(S698PM_IPI_IRQ, s698pm_pause_handler, NULL); + irq_attach(S698PM_IPI_IRQ, s698pm_smp_call_handler, NULL); (void)s698pm_setup_irq(cpu, S698PM_IPI_IRQ, 0); diff --git a/arch/sparc/src/s698pm/s698pm.h b/arch/sparc/src/s698pm/s698pm.h index 6182b23855..0686e3fdc2 100644 --- a/arch/sparc/src/s698pm/s698pm.h +++ b/arch/sparc/src/s698pm/s698pm.h @@ -416,21 +416,15 @@ void gpio_irqdisable(int irq); #endif /**************************************************************************** - * Name: s698pm_pause_handler + * Name: s698pm_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ #ifdef CONFIG_SMP -int s698pm_pause_handler(int irq, void *c, void *arg); +int s698pm_smp_call_handler(int irq, void *c, void *arg); #endif #undef EXTERN diff --git a/arch/sparc/src/s698pm/s698pm_cpupause.c b/arch/sparc/src/s698pm/s698pm_smpcall.c similarity index 90% rename from arch/sparc/src/s698pm/s698pm_cpupause.c rename to arch/sparc/src/s698pm/s698pm_smpcall.c index a9b9b570f6..c08272d722 100644 --- a/arch/sparc/src/s698pm/s698pm_cpupause.c +++ b/arch/sparc/src/s698pm/s698pm_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/sparc/src/s698pm/s698pm_cpupause.c + * arch/sparc/src/s698pm/s698pm_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -47,20 +47,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: s698pm_pause_handler + * Name: s698pm_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int s698pm_pause_handler(int irq, void *c, void *arg) +int s698pm_smp_call_handler(int irq, void *c, void *arg) { struct tcb_s *tcb; int cpu = this_cpu(); @@ -80,7 +74,7 @@ int s698pm_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -98,7 +92,7 @@ int s698pm_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { uintptr_t regaddr; @@ -131,6 +125,6 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } } diff --git a/arch/x86_64/include/intel64/irq.h b/arch/x86_64/include/intel64/irq.h index f4831c05b9..ebb178e0b3 100644 --- a/arch/x86_64/include/intel64/irq.h +++ b/arch/x86_64/include/intel64/irq.h @@ -352,8 +352,8 @@ /* Use IRQ24 IRQ25 for SMP */ -#define SMP_IPI_IRQ IRQ24 -#define SMP_IPI_ASYNC_IRQ IRQ25 +#define SMP_IPI_CALL_IRQ IRQ24 +#define SMP_IPI_SCHED_IRQ IRQ25 /* Use IRQ32 and above for MSI */ diff --git a/arch/x86_64/src/intel64/CMakeLists.txt b/arch/x86_64/src/intel64/CMakeLists.txt index f5b1a76977..d92242b5e0 100644 --- a/arch/x86_64/src/intel64/CMakeLists.txt +++ b/arch/x86_64/src/intel64/CMakeLists.txt @@ -57,7 +57,7 @@ if(CONFIG_ARCH_HAVE_TESTSET) endif() if(CONFIG_SMP) - list(APPEND SRCS intel64_cpuidlestack.c intel64_cpupause.c intel64_cpustart.c) + list(APPEND SRCS intel64_cpuidlestack.c intel64_smpcall.c intel64_cpustart.c) endif() if(CONFIG_MULTBOOT2_FB_TERM) diff --git a/arch/x86_64/src/intel64/Make.defs b/arch/x86_64/src/intel64/Make.defs index e1c8579c97..1fc6f1de52 100644 --- a/arch/x86_64/src/intel64/Make.defs +++ b/arch/x86_64/src/intel64/Make.defs @@ -44,7 +44,7 @@ endif ifeq ($(CONFIG_SMP),y) CHIP_CSRCS += intel64_cpuidlestack.c -CHIP_CSRCS += intel64_cpupause.c +CHIP_CSRCS += intel64_smpcall.c CHIP_CSRCS += intel64_cpustart.c endif diff --git a/arch/x86_64/src/intel64/intel64_cpustart.c b/arch/x86_64/src/intel64/intel64_cpustart.c index 7a71125527..efd347982b 100644 --- a/arch/x86_64/src/intel64/intel64_cpustart.c +++ b/arch/x86_64/src/intel64/intel64_cpustart.c @@ -47,8 +47,8 @@ ****************************************************************************/ extern void __ap_entry(void); -extern int up_pause_handler(int irq, void *c, void *arg); -extern int up_pause_async_handler(int irq, void *c, void *arg); +extern int x86_64_smp_call_handler(int irq, void *c, void *arg); +extern int x86_64_smp_sched_handler(int irq, void *c, void *arg); /**************************************************************************** * Private Functions @@ -164,10 +164,10 @@ void x86_64_ap_boot(void) /* Connect Pause IRQ to CPU */ - irq_attach(SMP_IPI_IRQ, up_pause_handler, NULL); - irq_attach(SMP_IPI_ASYNC_IRQ, up_pause_async_handler, NULL); - up_enable_irq(SMP_IPI_IRQ); - up_enable_irq(SMP_IPI_ASYNC_IRQ); + irq_attach(SMP_IPI_CALL_IRQ, x86_64_smp_call_handler, NULL); + irq_attach(SMP_IPI_SCHED_IRQ, x86_64_smp_sched_handler, NULL); + up_enable_irq(SMP_IPI_CALL_IRQ); + up_enable_irq(SMP_IPI_SCHED_IRQ); #ifdef CONFIG_STACK_COLORATION /* If stack debug is enabled, then fill the stack with a diff --git a/arch/x86_64/src/intel64/intel64_cpupause.c b/arch/x86_64/src/intel64/intel64_smpcall.c similarity index 87% rename from arch/x86_64/src/intel64/intel64_cpupause.c rename to arch/x86_64/src/intel64/intel64_smpcall.c index a1932e615b..24f23d8e2f 100644 --- a/arch/x86_64/src/intel64/intel64_cpupause.c +++ b/arch/x86_64/src/intel64/intel64_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/x86_64/src/intel64/intel64_cpupause.c + * arch/x86_64/src/intel64/intel64_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -49,20 +49,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: up_pause_handler + * Name: x86_64_smp_call_handler * * Description: - * Inter-CPU interrupt handler - * - * Input Parameters: - * Standard interrupt handler inputs - * - * Returned Value: - * Should always return OK + * This is the handler for SMP_CALL. * ****************************************************************************/ -int up_pause_handler(int irq, void *c, void *arg) +int x86_64_smp_call_handler(int irq, void *c, void *arg) { struct tcb_s *tcb; int cpu = this_cpu(); @@ -77,10 +71,10 @@ int up_pause_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_pause_async_handler + * Name: x86_64_smp_sched_handler * * Description: - * This is the handler for async pause. + * This is the handler for smp. * * 1. It saves the current task state at the head of the current assigned * task list. @@ -96,7 +90,7 @@ int up_pause_handler(int irq, void *c, void *arg) * ****************************************************************************/ -int up_pause_async_handler(int irq, void *c, void *arg) +int x86_64_smp_sched_handler(int irq, void *c, void *arg) { struct tcb_s *tcb; int cpu = this_cpu(); @@ -113,7 +107,7 @@ int up_pause_async_handler(int irq, void *c, void *arg) } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -131,14 +125,14 @@ int up_pause_async_handler(int irq, void *c, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { cpu_set_t cpuset; CPU_ZERO(&cpuset); CPU_SET(cpu, &cpuset); - up_trigger_irq(SMP_IPI_ASYNC_IRQ, cpuset); + up_trigger_irq(SMP_IPI_SCHED_IRQ, cpuset); return OK; } @@ -159,5 +153,5 @@ inline_function int up_cpu_pause_async(int cpu) void up_send_smp_call(cpu_set_t cpuset) { - up_trigger_irq(SMP_IPI_IRQ, cpuset); + up_trigger_irq(SMP_IPI_CALL_IRQ, cpuset); } diff --git a/arch/xtensa/src/common/Make.defs b/arch/xtensa/src/common/Make.defs index 46997a6e78..061575726b 100644 --- a/arch/xtensa/src/common/Make.defs +++ b/arch/xtensa/src/common/Make.defs @@ -53,7 +53,7 @@ ifeq ($(CONFIG_SCHED_BACKTRACE),y) endif ifeq ($(CONFIG_SMP),y) - CMN_CSRCS += xtensa_cpupause.c + CMN_CSRCS += xtensa_smpcall.c endif ifeq ($(CONFIG_STACK_COLORATION),y) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index ea776419d4..f0eb3a5ff3 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -234,7 +234,7 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs); #ifdef CONFIG_SMP int xtensa_intercpu_interrupt(int tocpu, int intcode); -void xtensa_pause_handler(int irq, void *context, void *arg); +void xtensa_smp_call_handler(int irq, void *context, void *arg); #endif /* Signals */ diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_smpcall.c similarity index 79% rename from arch/xtensa/src/common/xtensa_cpupause.c rename to arch/xtensa/src/common/xtensa_smpcall.c index 287b93b568..f92f442e2f 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_smpcall.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_cpupause.c + * arch/xtensa/src/common/xtensa_smpcall.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -46,34 +46,21 @@ ****************************************************************************/ /**************************************************************************** - * Name: xtensa_pause_handler + * Name: xtensa_smp_call_handler * * Description: - * This is the handler for CPU_INTCODE_PAUSE CPU interrupt. This - * implements up_cpu_pause() by performing the following operations: - * - * 1. The current task state at the head of the current assigned task - * list was saved when the interrupt was entered. - * 2. This function simply waits on a spinlock, then returns. - * 3. Upon return, the interrupt exit logic will restore the state of - * the new task at the head of the ready to run list. - * - * Input Parameters: - * None - * - * Returned Value: - * None + * This is the handler for smp. * ****************************************************************************/ -void xtensa_pause_handler(int irq, void *context, void *arg) +void xtensa_smp_call_handler(int irq, void *context, void *arg) { nxsched_smp_call_handler(irq, context, arg); nxsched_process_delivered(this_cpu()); } /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -91,7 +78,7 @@ void xtensa_pause_handler(int irq, void *context, void *arg) * ****************************************************************************/ -inline_function int up_cpu_pause_async(int cpu) +int up_send_smp_sched(int cpu) { /* Execute the intercpu interrupt */ @@ -121,7 +108,7 @@ void up_send_smp_call(cpu_set_t cpuset) for (; cpuset != 0; cpuset &= ~(1 << cpu)) { cpu = ffs(cpuset) - 1; - xtensa_intercpu_interrupt(cpu, CPU_INTCODE_PAUSE); + up_send_smp_sched(cpu); } } diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c index 68f602d083..96e189bc86 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -63,9 +63,9 @@ static int IRAM_ATTR esp32_fromcpu_interrupt(int irq, void *context, DPORT_CPU_INTR_FROM_CPU_1_REG; putreg32(0, regaddr); - /* Call pause handler */ + /* Smp call handler */ - xtensa_pause_handler(irq, context, arg); + xtensa_smp_call_handler(irq, context, arg); return OK; } diff --git a/arch/xtensa/src/esp32s3/esp32s3_intercpu_interrupt.c b/arch/xtensa/src/esp32s3/esp32s3_intercpu_interrupt.c index 60891afee8..52ed92e0dd 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32s3/esp32s3_intercpu_interrupt.c @@ -64,9 +64,9 @@ static int IRAM_ATTR esp32s3_fromcpu_interrupt(int irq, void *context, SYSTEM_CPU_INTR_FROM_CPU_1_REG; putreg32(0, regaddr); - /* Call pause handler */ + /* Smp call handler */ - xtensa_pause_handler(irq, context, arg); + xtensa_smp_call_handler(irq, context, arg); return OK; } diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 4edd69ce04..c9b46b1265 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -1744,18 +1744,6 @@ void up_secure_irq(int irq, bool secure); # define up_secure_irq(i, s) #endif -#ifdef CONFIG_SMP -/**************************************************************************** - * Name: up_send_smp_call - * - * Description: - * Send smp call to target cpu - * - ****************************************************************************/ - -void up_send_smp_call(cpu_set_t cpuset); -#endif - /**************************************************************************** * Name: up_secure_irq_all * @@ -2288,8 +2276,9 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size); int up_cpu_start(int cpu); #endif +#ifdef CONFIG_SMP /**************************************************************************** - * Name: up_cpu_pause_async + * Name: up_send_smp_sched * * Description: * pause task execution on the CPU @@ -2307,8 +2296,17 @@ int up_cpu_start(int cpu); * ****************************************************************************/ -#ifdef CONFIG_SMP -int up_cpu_pause_async(int cpu); +int up_send_smp_sched(int cpu); + +/**************************************************************************** + * Name: up_send_smp_call + * + * Description: + * Send smp call to target cpu + * + ****************************************************************************/ + +void up_send_smp_call(cpu_set_t cpuset); #endif /**************************************************************************** diff --git a/sched/sched/sched_addreadytorun.c b/sched/sched/sched_addreadytorun.c index 79c66a9912..18032dc9b4 100644 --- a/sched/sched/sched_addreadytorun.c +++ b/sched/sched/sched_addreadytorun.c @@ -233,7 +233,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) g_delivertasks[cpu] = btcb; btcb->cpu = cpu; btcb->task_state = TSTATE_TASK_ASSIGNED; - up_cpu_pause_async(cpu); + up_send_smp_sched(cpu); } else {
