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commit 7288a8d0009460234e7f9166ef1a1e5509c41447 Author: chao an <[email protected]> AuthorDate: Mon Oct 14 12:33:50 2024 +0800 arch/arm64: add support to config SPI interrupt affinity routing to CPU0 by default Signed-off-by: chao an <[email protected]> --- arch/arm64/Kconfig | 7 +++++++ arch/arm64/src/common/arm64_arch.h | 2 +- arch/arm64/src/common/arm64_gicv3.c | 13 +++++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8aa8681902..fc30a757dc 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -361,6 +361,13 @@ config ARM64_GICV3_SPI_EDGE ---help--- Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default. +config ARM64_GICV3_SPI_ROUTING_CPU0 + bool "Configure SPI interrupt affinity routing to CPU0 by default" + default y if SMP + default n + ---help--- + Configure SPI interrupt affinity routing to CPU0 by default. + endif config ARM64_SEMIHOSTING_HOSTFS diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h index fbd47f5437..fdbd74a55d 100644 --- a/arch/arm64/src/common/arm64_arch.h +++ b/arch/arm64/src/common/arm64_arch.h @@ -506,7 +506,7 @@ void arm64_cpu_enable(void); #ifdef CONFIG_SMP uint64_t arm64_get_mpid(int cpu); #else -# define arm64_get_mpid(cpu) GET_MPIDR() +# define arm64_get_mpid(cpu) (GET_MPIDR() & MPIDR_ID_MASK) #endif /* CONFIG_SMP */ /**************************************************************************** diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c index 9b0d2985fb..3e52e17bfe 100644 --- a/arch/arm64/src/common/arm64_gicv3.c +++ b/arch/arm64/src/common/arm64_gicv3.c @@ -254,10 +254,12 @@ void arm64_gic_irq_enable(unsigned int intid) * SPI's affinity, now set it to be the PE on which it is enabled. */ +#ifndef CONFIG_ARM64_GICV3_SPI_ROUTING_CPU0 if (GIC_IS_SPI(intid)) { arm64_gic_write_irouter((GET_MPIDR() & MPIDR_ID_MASK), intid); } +#endif putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx)); } @@ -618,6 +620,17 @@ static void gicv3_dist_init(void) #endif } + /* Configure SPI interrupt affinity routing to CPU0 */ + +#ifdef CONFIG_ARM64_GICV3_SPI_ROUTING_CPU0 + uint64_t mpid = arm64_get_mpid(0); + + for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid++) + { + putreg64(mpid, IROUTER(base, intid)); + } +#endif + /* TODO: Some arrch64 Cortex-A core maybe without security state * it has different GIC configure with standard arrch64 A or R core */
