This is an automated email from the ASF dual-hosted git repository. xiaoxiang pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 4e2b77cb048d433b508cf63349d83e5135ce1cc0 Author: buxiasen <[email protected]> AuthorDate: Thu Oct 17 12:18:05 2024 +0800 arch/arm: add support for chip to replace the default vector table Signed-off-by: buxiasen <[email protected]> --- arch/Kconfig | 7 +++++++ arch/arm/src/armv6-m/Make.defs | 6 +++++- arch/arm/src/armv7-m/Make.defs | 6 +++++- arch/arm/src/armv8-m/Make.defs | 6 +++++- 4 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index d895e04b52..4f63fbbbfc 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1119,6 +1119,13 @@ config ARCH_RAMFUNCS so that FLASH can be reconfigured while the MCU executes out of SRAM. +config ARCH_HAVE_CUSTOM_VECTORS + bool + default n + ---help--- + If ARCH_HAVE_CUSTOM_VECTORS is defined, Chip should provide vectors + table as an optimization. + config ARCH_HAVE_RAMVECTORS bool default n diff --git a/arch/arm/src/armv6-m/Make.defs b/arch/arm/src/armv6-m/Make.defs index 287ef74ac0..504741f428 100644 --- a/arch/arm/src/armv6-m/Make.defs +++ b/arch/arm/src/armv6-m/Make.defs @@ -26,9 +26,13 @@ CMN_ASRCS += arm_exception.S arm_saveusercontext.S CMN_CSRCS += arm_cpuinfo.c arm_doirq.c arm_hardfault.c arm_initialstate.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c -CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c arm_vectors.c +CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c CMN_CSRCS += arm_trigger_irq.c +ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y) + CMN_CSRCS += arm_vectors.c +endif + ifneq ($(filter y,$(CONFIG_DEBUG_FEATURES)$(CONFIG_ARM_COREDUMP_REGION)),) CMN_CSRCS += arm_dumpnvic.c endif diff --git a/arch/arm/src/armv7-m/Make.defs b/arch/arm/src/armv7-m/Make.defs index 85f3a9af48..feccc61bc6 100644 --- a/arch/arm/src/armv7-m/Make.defs +++ b/arch/arm/src/armv7-m/Make.defs @@ -29,7 +29,11 @@ CMN_CSRCS += arm_hardfault.c arm_initialstate.c arm_itm.c CMN_CSRCS += arm_memfault.c arm_perf.c CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c -CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c arm_dbgmonitor.c +CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_dbgmonitor.c + +ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y) + CMN_CSRCS += arm_vectors.c +endif ifeq ($(CONFIG_ARMV7M_SYSTICK),y) CMN_CSRCS += arm_systick.c diff --git a/arch/arm/src/armv8-m/Make.defs b/arch/arm/src/armv8-m/Make.defs index cec4256f62..e15806a2d4 100644 --- a/arch/arm/src/armv8-m/Make.defs +++ b/arch/arm/src/armv8-m/Make.defs @@ -30,7 +30,11 @@ CMN_CSRCS += arm_memfault.c arm_perf.c arm_sau.c CMN_CSRCS += arm_schedulesigaction.c arm_securefault.c arm_secure_irq.c CMN_CSRCS += arm_sigdeliver.c arm_svcall.c CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c -CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c arm_dbgmonitor.c +CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_dbgmonitor.c + +ifneq ($(CONFIG_ARCH_HAVE_CUSTOM_VECTORS),y) + CMN_CSRCS += arm_vectors.c +endif ifeq ($(CONFIG_ARMV8M_SYSTICK),y) CMN_CSRCS += arm_systick.c
