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commit 6f8953ed0b0ae1f9bfae2caee1489d5d7eba724a Author: raiden00pl <[email protected]> AuthorDate: Sun Oct 20 17:20:05 2024 +0200 boards/arm/stm32f7: move SPI test logic to common move STM32F7 SPI test logic to common --- boards/arm/stm32f7/common/Kconfig | 153 ++++++++++++++++++ boards/arm/stm32f7/common/include/stm32_spitest.h | 74 +++++++++ boards/arm/stm32f7/common/src/CMakeLists.txt | 4 + boards/arm/stm32f7/common/src/Make.defs | 4 + boards/arm/stm32f7/common/src/stm32_spitest.c | 174 +++++++++++++++++++++ boards/arm/stm32f7/nucleo-f722ze/Kconfig | 154 ------------------ .../arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h | 13 -- .../arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c | 8 +- boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c | 119 -------------- boards/arm/stm32f7/nucleo-f746zg/Kconfig | 154 ------------------ .../arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c | 8 +- boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c | 119 -------------- boards/arm/stm32f7/nucleo-f767zi/Kconfig | 154 ------------------ .../arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c | 8 +- boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c | 119 -------------- 15 files changed, 427 insertions(+), 838 deletions(-) diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig index 5d02131b7f..2d926e6634 100644 --- a/boards/arm/stm32f7/common/Kconfig +++ b/boards/arm/stm32f7/common/Kconfig @@ -25,3 +25,156 @@ config STM32F7_ROMFS_IMAGEFILE depends on STM32F7_ROMFS default "../../../rom.img" +config STM32F7_SPI_TEST + bool "Enable SPI test" + default n + ---help--- + Enable Spi test - initialize and configure SPI to send + STM32F7_SPI_TEST_MESSAGE text. The text is sent on the + selected SPI Buses with the configured parameters. + Note the CS lines will not be asserted. + +if STM32F7_SPI_TEST + +config STM32F7_SPI_TEST_MESSAGE + string "Text to Send on SPI Bus(es)" + default "Hello World" + depends on STM32F7_SPI_TEST + ---help--- + Text to sent on SPI bus(es) + +config STM32F7_SPI1_TEST + bool "Test SPI bus 1" + default n + depends on STM32F7_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 1 + +if STM32F7_SPI1_TEST + +config STM32F7_SPI1_TEST_FREQ + int "SPI 1 Clock Freq in Hz" + default 1000000 + depends on STM32F7_SPI1_TEST + ---help--- + Sets SPI 1 Clock Freq + +config STM32F7_SPI1_TEST_BITS + int "SPI 1 number of bits" + default 8 + depends on STM32F7_SPI1_TEST + ---help--- + Sets SPI 1 bit length + +choice + prompt "SPI BUS 1 Clock Mode" + default STM32F7_SPI1_TEST_MODE3 + ---help--- + Sets SPI 1 clock mode + +config STM32F7_SPI1_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32F7_SPI1_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32F7_SPI1_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32F7_SPI1_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 1 Clock Mode" + +endif # STM32F7_SPI1_TEST + +config STM32F7_SPI2_TEST + bool "Test SPI bus 2" + default n + depends on STM32F7_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 2 + +if STM32F7_SPI2_TEST + +config STM32F7_SPI2_TEST_FREQ + int "SPI 2 Clock Freq in Hz" + default 12000000 + depends on STM32F7_SPI2_TEST + ---help--- + Sets SPI 2 Clock Freq + +config STM32F7_SPI2_TEST_BITS + int "SPI 2 number of bits" + default 8 + depends on STM32F7_SPI2_TEST + ---help--- + Sets SPI 2 bit length + +choice + prompt "SPI BUS 2 Clock Mode" + default STM32F7_SPI2_TEST_MODE3 + ---help--- + Sets SPI 2 clock mode + +config STM32F7_SPI2_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32F7_SPI2_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32F7_SPI2_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32F7_SPI2_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 2 Clock Mode" + +endif # STM32F7_SPI2_TEST + +config STM32F7_SPI3_TEST + bool "Test SPI bus 3" + default n + depends on STM32F7_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 3 + +if STM32F7_SPI3_TEST + +config STM32F7_SPI3_TEST_FREQ + int "SPI 3 Clock Freq in Hz" + default 40000000 + depends on STM32F7_SPI3_TEST + ---help--- + Sets SPI 3 Clock Freq + +config STM32F7_SPI3_TEST_BITS + int "SPI 3 number of bits" + default 8 + depends on STM32F7_SPI3_TEST + ---help--- + Sets SPI 3 bit length + +choice + prompt "SPI BUS 3 Clock Mode" + default STM32F7_SPI3_TEST_MODE3 + ---help--- + Sets SPI 3 clock mode + +config STM32F7_SPI3_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32F7_SPI3_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32F7_SPI3_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32F7_SPI3_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 3 Clock Mode" + +endif # STM32F7_SPI3_TEST +endif # STM32F7_SPI_TEST diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/stm32f7/common/include/stm32_spitest.h new file mode 100644 index 0000000000..f7db5e4431 --- /dev/null +++ b/boards/arm/stm32f7/common/include/stm32_spitest.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/arm/stm32f7/common/include/stm32_spitest.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H +#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_bus_test + * + * Description: + * Called to create the defined SPI buses and test them by initializing + * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * + ****************************************************************************/ + +int stm32_spidev_bus_test(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H */ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt index 4c99128057..be18e09d37 100644 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ b/boards/arm/stm32f7/common/src/CMakeLists.txt @@ -49,4 +49,8 @@ if(CONFIG_BOARDCTL_RESET) list(APPEND SRCS stm32_reset.c) endif() +if(CONFIG_STM32F7_SPI_TEST) + list(APPEND SRCS stm32_spitest.c) +endif() + target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs index 2f1a7b4544..b3df0015a5 100644 --- a/boards/arm/stm32f7/common/src/Make.defs +++ b/boards/arm/stm32f7/common/src/Make.defs @@ -49,6 +49,10 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += stm32_reset.c endif +ifeq ($(CONFIG_STM32F7_SPI_TEST),y) +CSRCS += stm32_spitest.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c new file mode 100644 index 0000000000..8cf5536b77 --- /dev/null +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -0,0 +1,174 @@ +/**************************************************************************** + * boards/arm/stm32f7/common/src/stm32_spitest.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <errno.h> +#include <debug.h> + +#include <sys/param.h> + +#include <nuttx/spi/spi.h> +#include <arch/board/board.h> + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SPI1_TEST) +# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0) +# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1) +# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2) +# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3) +# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_STM32F7_SPI2_TEST) +# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0) +# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1) +# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2) +# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3) +# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_STM32F7_SPI3_TEST) +# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0) +# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1) +# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2) +# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3) +# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SPI1) +struct spi_dev_s *g_spi1; +#endif +#if defined(CONFIG_STM32F7_SPI2) +struct spi_dev_s *g_spi2; +#endif +#if defined(CONFIG_STM32F7_SPI3) +struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_bus_test + * + * Description: + * Called to create the defined SPI buses and test them by initializing + * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * + ****************************************************************************/ + +int stm32_spidev_bus_test(void) +{ + /* Configure and test SPI- */ + + uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE; + +#if defined(CONFIG_STM32F7_SPI1_TEST) + g_spi1 = stm32_spibus_initialize(1); + + if (!g_spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); + SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); + SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); + SPI_EXCHANGE(g_spi1, tx, NULL, + nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_STM32F7_SPI2_TEST) + g_spi2 = stm32_spibus_initialize(2); + + if (!g_spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); + SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); + SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); + SPI_EXCHANGE(g_spi2, tx, NULL, + nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_STM32F7_SPI3_TEST) + g_spi3 = stm32_spibus_initialize(3); + + if (!g_spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); + SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); + SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); + SPI_EXCHANGE(g_spi3, tx, NULL, + nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); +#endif + + return OK; +} diff --git a/boards/arm/stm32f7/nucleo-f722ze/Kconfig b/boards/arm/stm32f7/nucleo-f722ze/Kconfig index c34fa5de59..cc1912c99a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/Kconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/Kconfig @@ -80,160 +80,6 @@ config NUCLEO_F722ZE_CONSOLE_NONE endchoice # "Select Console wiring" -config NUCLEO_F722ZE_SPI_TEST - bool "Enable SPI test" - default n - ---help--- - Enable Spi test - initialize and configure SPI to send - NUCLEO_F722ZE_SPI_TEST_MESSAGE text. The text is sent on the - selected SPI Buses with the configured parameters. - Note the CS lines will not be asserted. - -if NUCLEO_F722ZE_SPI_TEST - -config NUCLEO_F722ZE_SPI_TEST_MESSAGE - string "Text to Send on SPI Bus(es)" - default "Hello World" - depends on NUCLEO_F722ZE_SPI_TEST - ---help--- - Text to sent on SPI bus(es) - -config NUCLEO_F722ZE_SPI1_TEST - bool "Test SPI bus 1" - default n - depends on NUCLEO_F722ZE_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 1 - -if NUCLEO_F722ZE_SPI1_TEST - -config NUCLEO_F722ZE_SPI1_TEST_FREQ - int "SPI 1 Clock Freq in Hz" - default 1000000 - depends on NUCLEO_F722ZE_SPI1_TEST - ---help--- - Sets SPI 1 Clock Freq - -config NUCLEO_F722ZE_SPI1_TEST_BITS - int "SPI 1 number of bits" - default 8 - depends on NUCLEO_F722ZE_SPI1_TEST - ---help--- - Sets SPI 1 bit length - -choice - prompt "SPI BUS 1 Clock Mode" - default NUCLEO_F722ZE_SPI1_TEST_MODE3 - ---help--- - Sets SPI 1 clock mode - -config NUCLEO_F722ZE_SPI1_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F722ZE_SPI1_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F722ZE_SPI1_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F722ZE_SPI1_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 1 Clock Mode" - -endif # NUCLEO_F722ZE_SPI1_TEST - -config NUCLEO_F722ZE_SPI2_TEST - bool "Test SPI bus 2" - default n - depends on NUCLEO_F722ZE_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 2 - -if NUCLEO_F722ZE_SPI2_TEST - -config NUCLEO_F722ZE_SPI2_TEST_FREQ - int "SPI 2 Clock Freq in Hz" - default 12000000 - depends on NUCLEO_F722ZE_SPI2_TEST - ---help--- - Sets SPI 2 Clock Freq - -config NUCLEO_F722ZE_SPI2_TEST_BITS - int "SPI 2 number of bits" - default 8 - depends on NUCLEO_F722ZE_SPI2_TEST - ---help--- - Sets SPI 2 bit length - -choice - prompt "SPI BUS 2 Clock Mode" - default NUCLEO_F722ZE_SPI2_TEST_MODE3 - ---help--- - Sets SPI 2 clock mode - -config NUCLEO_F722ZE_SPI2_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F722ZE_SPI2_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F722ZE_SPI2_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F722ZE_SPI2_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 2 Clock Mode" - -endif # NUCLEO_F722ZE_SPI2_TEST - -config NUCLEO_F722ZE_SPI3_TEST - bool "Test SPI bus 3" - default n - depends on NUCLEO_F722ZE_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 3 - -if NUCLEO_F722ZE_SPI3_TEST - -config NUCLEO_F722ZE_SPI3_TEST_FREQ - int "SPI 3 Clock Freq in Hz" - default 40000000 - depends on NUCLEO_F722ZE_SPI3_TEST - ---help--- - Sets SPI 3 Clock Freq - -config NUCLEO_F722ZE_SPI3_TEST_BITS - int "SPI 3 number of bits" - default 8 - depends on NUCLEO_F722ZE_SPI3_TEST - ---help--- - Sets SPI 3 bit length - -choice - prompt "SPI BUS 3 Clock Mode" - default NUCLEO_F722ZE_SPI3_TEST_MODE3 - ---help--- - Sets SPI 3 clock mode - -config NUCLEO_F722ZE_SPI3_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F722ZE_SPI3_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F722ZE_SPI3_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F722ZE_SPI3_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 3 Clock Mode" - -endif # NUCLEO_F722ZE_SPI3_TEST -endif # NUCLEO_F722ZE_SPI_TEST - choice prompt "CAN1 pins selection" default NUCLEO_F722ZE_CAN1_MAP_PD0PD1 diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 5b45185c3d..6be7dda102 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -229,19 +229,6 @@ int stm32_bringup(void); void stm32_spidev_initialize(void); #endif -/**************************************************************************** - * Name: stm32_spidev_bus_test - * - * Description: - * Called to create the defined SPI buses and test them by initializing - * them and sending the NUCLEO_SPI_TEST (no chip select). - * - ****************************************************************************/ - -#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST) -int stm32_spidev_bus_test(void); -#endif - /**************************************************************************** * Name: stm32_dma_alloc_init * diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c index 473460b5ed..25286cd599 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c @@ -50,8 +50,12 @@ # include "stm32_romfs.h" #endif +#ifdef CONFIG_STM32F7_SPI_TEST +# include "stm32_spitest.h" +#endif + #ifdef CONFIG_SYSTEMTICK_HOOK -#include <semaphore.h> +# include <semaphore.h> #endif /**************************************************************************** @@ -149,7 +153,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST) +#ifdef CONFIG_STM32F7_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c index e05e28fa8c..81af1eb8d3 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c @@ -47,48 +47,6 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST) -# if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE0) -# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE1) -# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE2) -# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE3) -# define CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST) -# if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE0) -# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE1) -# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE2) -# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE3) -# define CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST) -# if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE0) -# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE1) -# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE2) -# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE3) -# define CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODEx defined" -# endif -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] = }; #endif -#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST) -# if defined(CONFIG_STM32F7_SPI1) -struct spi_dev_s *spi1; -# endif -# if defined(CONFIG_STM32F7_SPI2) -struct spi_dev_s *spi2; -# endif -# if defined(CONFIG_STM32F7_SPI3) -struct spi_dev_s *spi3; -# endif -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ - -#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST) -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI- */ - - uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE; - -#if defined(CONFIG_NUCLEO_F722ZE_SPI1_TEST) - spi1 = stm32_spibus_initialize(1); - - if (!spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_FREQ); - SPI_SETBITS(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_BITS); - SPI_SETMODE(spi1, CONFIG_NUCLEO_F722ZE_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, - nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F722ZE_SPI2_TEST) - spi2 = stm32_spibus_initialize(2); - - if (!spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_FREQ); - SPI_SETBITS(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_BITS); - SPI_SETMODE(spi2, CONFIG_NUCLEO_F722ZE_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, - nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F722ZE_SPI3_TEST) - spi3 = stm32_spibus_initialize(3); - - if (!spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_FREQ); - SPI_SETBITS(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_BITS); - SPI_SETMODE(spi3, CONFIG_NUCLEO_F722ZE_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, - nitems(CONFIG_NUCLEO_F722ZE_SPI_TEST_MESSAGE)); -#endif - - return OK; -} -#endif /* NUCLEO_SPI_TEST */ #endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/Kconfig b/boards/arm/stm32f7/nucleo-f746zg/Kconfig index 6697898410..4f7bdfdbe7 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/Kconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/Kconfig @@ -80,160 +80,6 @@ config NUCLEO_F746ZG_CONSOLE_NONE endchoice # "Select Console wiring" -config NUCLEO_F746ZG_SPI_TEST - bool "Enable SPI test" - default n - ---help--- - Enable Spi test - initialize and configure SPI to send - NUCLEO_F746ZG_SPI_TEST_MESSAGE text. The text is sent on the - selected SPI Buses with the configured parameters. - Note the CS lines will not be asserted. - -if NUCLEO_F746ZG_SPI_TEST - -config NUCLEO_F746ZG_SPI_TEST_MESSAGE - string "Text to Send on SPI Bus(es)" - default "Hello World" - depends on NUCLEO_F746ZG_SPI_TEST - ---help--- - Text to sent on SPI bus(es) - -config NUCLEO_F746ZG_SPI1_TEST - bool "Test SPI bus 1" - default n - depends on NUCLEO_F746ZG_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 1 - -if NUCLEO_F746ZG_SPI1_TEST - -config NUCLEO_F746ZG_SPI1_TEST_FREQ - int "SPI 1 Clock Freq in Hz" - default 1000000 - depends on NUCLEO_F746ZG_SPI1_TEST - ---help--- - Sets SPI 1 Clock Freq - -config NUCLEO_F746ZG_SPI1_TEST_BITS - int "SPI 1 number of bits" - default 8 - depends on NUCLEO_F746ZG_SPI1_TEST - ---help--- - Sets SPI 1 bit length - -choice - prompt "SPI BUS 1 Clock Mode" - default NUCLEO_F746ZG_SPI1_TEST_MODE3 - ---help--- - Sets SPI 1 clock mode - -config NUCLEO_F746ZG_SPI1_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F746ZG_SPI1_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F746ZG_SPI1_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F746ZG_SPI1_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 1 Clock Mode" - -endif # NUCLEO_F746ZG_SPI1_TEST - -config NUCLEO_F746ZG_SPI2_TEST - bool "Test SPI bus 2" - default n - depends on NUCLEO_F746ZG_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 2 - -if NUCLEO_F746ZG_SPI2_TEST - -config NUCLEO_F746ZG_SPI2_TEST_FREQ - int "SPI 2 Clock Freq in Hz" - default 12000000 - depends on NUCLEO_F746ZG_SPI2_TEST - ---help--- - Sets SPI 2 Clock Freq - -config NUCLEO_F746ZG_SPI2_TEST_BITS - int "SPI 2 number of bits" - default 8 - depends on NUCLEO_F746ZG_SPI2_TEST - ---help--- - Sets SPI 2 bit length - -choice - prompt "SPI BUS 2 Clock Mode" - default NUCLEO_F746ZG_SPI2_TEST_MODE3 - ---help--- - Sets SPI 2 clock mode - -config NUCLEO_F746ZG_SPI2_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F746ZG_SPI2_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F746ZG_SPI2_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F746ZG_SPI2_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 2 Clock Mode" - -endif # NUCLEO_F746ZG_SPI2_TEST - -config NUCLEO_F746ZG_SPI3_TEST - bool "Test SPI bus 3" - default n - depends on NUCLEO_F746ZG_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 3 - -if NUCLEO_F746ZG_SPI3_TEST - -config NUCLEO_F746ZG_SPI3_TEST_FREQ - int "SPI 3 Clock Freq in Hz" - default 40000000 - depends on NUCLEO_F746ZG_SPI3_TEST - ---help--- - Sets SPI 3 Clock Freq - -config NUCLEO_F746ZG_SPI3_TEST_BITS - int "SPI 3 number of bits" - default 8 - depends on NUCLEO_F746ZG_SPI3_TEST - ---help--- - Sets SPI 3 bit length - -choice - prompt "SPI BUS 3 Clock Mode" - default NUCLEO_F746ZG_SPI3_TEST_MODE3 - ---help--- - Sets SPI 3 clock mode - -config NUCLEO_F746ZG_SPI3_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F746ZG_SPI3_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F746ZG_SPI3_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F746ZG_SPI3_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 3 Clock Mode" - -endif # NUCLEO_F746ZG_SPI3_TEST -endif # NUCLEO_F746ZG_SPI_TEST - choice prompt "CAN1 pins selection" default NUCLEO_F746ZG_CAN1_MAP_PD0PD1 diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c index 5ef4a9699c..de0875f50f 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c @@ -50,8 +50,12 @@ # include "stm32_romfs.h" #endif +#ifdef CONFIG_STM32F7_SPI_TEST +# include "stm32_spitest.h" +#endif + #ifdef CONFIG_SYSTEMTICK_HOOK -#include <semaphore.h> +# include <semaphore.h> #endif /**************************************************************************** @@ -149,7 +153,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST) +#ifdef CONFIG_STM32F7_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c index 15cf08642c..743aeba7a5 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c @@ -47,48 +47,6 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST) -# if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE0) -# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE1) -# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE2) -# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE3) -# define CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST) -# if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE0) -# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE1) -# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE2) -# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE3) -# define CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST) -# if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE0) -# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE1) -# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE2) -# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE3) -# define CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODEx defined" -# endif -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] = }; #endif -#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST) -# if defined(CONFIG_STM32F7_SPI1) -struct spi_dev_s *spi1; -# endif -# if defined(CONFIG_STM32F7_SPI2) -struct spi_dev_s *spi2; -# endif -# if defined(CONFIG_STM32F7_SPI3) -struct spi_dev_s *spi3; -# endif -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ - -#if defined(CONFIG_NUCLEO_F746ZG_SPI_TEST) -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI- */ - - uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE; - -#if defined(CONFIG_NUCLEO_F746ZG_SPI1_TEST) - spi1 = stm32_spibus_initialize(1); - - if (!spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to NUCLEO_F746ZG_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_FREQ); - SPI_SETBITS(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_BITS); - SPI_SETMODE(spi1, CONFIG_NUCLEO_F746ZG_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, - nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F746ZG_SPI2_TEST) - spi2 = stm32_spibus_initialize(2); - - if (!spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to NUCLEO_F746ZG_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_FREQ); - SPI_SETBITS(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_BITS); - SPI_SETMODE(spi2, CONFIG_NUCLEO_F746ZG_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, - nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F746ZG_SPI3_TEST) - spi3 = stm32_spibus_initialize(3); - - if (!spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to NUCLEO_F746ZG_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_FREQ); - SPI_SETBITS(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_BITS); - SPI_SETMODE(spi3, CONFIG_NUCLEO_F746ZG_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, - nitems(CONFIG_NUCLEO_F746ZG_SPI_TEST_MESSAGE)); -#endif - - return OK; -} -#endif /* NUCLEO_F746ZG_SPI_TEST */ #endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/Kconfig b/boards/arm/stm32f7/nucleo-f767zi/Kconfig index d9cfd182bd..95614b8189 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/Kconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/Kconfig @@ -80,160 +80,6 @@ config NUCLEO_F767ZI_CONSOLE_NONE endchoice # "Select Console wiring" -config NUCLEO_F767ZI_SPI_TEST - bool "Enable SPI test" - default n - ---help--- - Enable Spi test - initialize and configure SPI to send - NUCLEO_F767ZI_SPI_TEST_MESSAGE text. The text is sent on the - selected SPI Buses with the configured parameters. - Note the CS lines will not be asserted. - -if NUCLEO_F767ZI_SPI_TEST - -config NUCLEO_F767ZI_SPI_TEST_MESSAGE - string "Text to Send on SPI Bus(es)" - default "Hello World" - depends on NUCLEO_F767ZI_SPI_TEST - ---help--- - Text to sent on SPI bus(es) - -config NUCLEO_F767ZI_SPI1_TEST - bool "Test SPI bus 1" - default n - depends on NUCLEO_F767ZI_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 1 - -if NUCLEO_F767ZI_SPI1_TEST - -config NUCLEO_F767ZI_SPI1_TEST_FREQ - int "SPI 1 Clock Freq in Hz" - default 1000000 - depends on NUCLEO_F767ZI_SPI1_TEST - ---help--- - Sets SPI 1 Clock Freq - -config NUCLEO_F767ZI_SPI1_TEST_BITS - int "SPI 1 number of bits" - default 8 - depends on NUCLEO_F767ZI_SPI1_TEST - ---help--- - Sets SPI 1 bit length - -choice - prompt "SPI BUS 1 Clock Mode" - default NUCLEO_F767ZI_SPI1_TEST_MODE3 - ---help--- - Sets SPI 1 clock mode - -config NUCLEO_F767ZI_SPI1_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F767ZI_SPI1_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F767ZI_SPI1_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F767ZI_SPI1_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 1 Clock Mode" - -endif # NUCLEO_F767ZI_SPI1_TEST - -config NUCLEO_F767ZI_SPI2_TEST - bool "Test SPI bus 2" - default n - depends on NUCLEO_F767ZI_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 2 - -if NUCLEO_F767ZI_SPI2_TEST - -config NUCLEO_F767ZI_SPI2_TEST_FREQ - int "SPI 2 Clock Freq in Hz" - default 12000000 - depends on NUCLEO_F767ZI_SPI2_TEST - ---help--- - Sets SPI 2 Clock Freq - -config NUCLEO_F767ZI_SPI2_TEST_BITS - int "SPI 2 number of bits" - default 8 - depends on NUCLEO_F767ZI_SPI2_TEST - ---help--- - Sets SPI 2 bit length - -choice - prompt "SPI BUS 2 Clock Mode" - default NUCLEO_F767ZI_SPI2_TEST_MODE3 - ---help--- - Sets SPI 2 clock mode - -config NUCLEO_F767ZI_SPI2_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F767ZI_SPI2_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F767ZI_SPI2_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F767ZI_SPI2_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 2 Clock Mode" - -endif # NUCLEO_F767ZI_SPI2_TEST - -config NUCLEO_F767ZI_SPI3_TEST - bool "Test SPI bus 3" - default n - depends on NUCLEO_F767ZI_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 3 - -if NUCLEO_F767ZI_SPI3_TEST - -config NUCLEO_F767ZI_SPI3_TEST_FREQ - int "SPI 3 Clock Freq in Hz" - default 40000000 - depends on NUCLEO_F767ZI_SPI3_TEST - ---help--- - Sets SPI 3 Clock Freq - -config NUCLEO_F767ZI_SPI3_TEST_BITS - int "SPI 3 number of bits" - default 8 - depends on NUCLEO_F767ZI_SPI3_TEST - ---help--- - Sets SPI 3 bit length - -choice - prompt "SPI BUS 3 Clock Mode" - default NUCLEO_F767ZI_SPI3_TEST_MODE3 - ---help--- - Sets SPI 3 clock mode - -config NUCLEO_F767ZI_SPI3_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config NUCLEO_F767ZI_SPI3_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config NUCLEO_F767ZI_SPI3_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config NUCLEO_F767ZI_SPI3_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 3 Clock Mode" - -endif # NUCLEO_F767ZI_SPI3_TEST -endif # NUCLEO_F767ZI_SPI_TEST - choice prompt "CAN1 pins selection" default NUCLEO_F767ZI_CAN1_MAP_PD0PD1 diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c index 2f32d07346..06c41c98ba 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c @@ -50,8 +50,12 @@ # include "stm32_romfs.h" #endif +#ifdef CONFIG_STM32F7_SPI_TEST +# include "stm32_spitest.h" +#endif + #ifdef CONFIG_SYSTEMTICK_HOOK -#include <semaphore.h> +# include <semaphore.h> #endif /**************************************************************************** @@ -149,7 +153,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_NUCLEO_F722ZE_SPI_TEST) +#ifdef CONFIG_STM32F7_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c index 4e346e1d82..1a4530c114 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c @@ -47,48 +47,6 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST) -# if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE0) -# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE1) -# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE2) -# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE3) -# define CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST) -# if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE0) -# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE1) -# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE2) -# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE3) -# define CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST) -# if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE0) -# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE1) -# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE2) -# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE3) -# define CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODEx defined" -# endif -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -171,18 +129,6 @@ static const uint32_t g_spi3gpio[] = }; #endif -#if defined(CONFIG_NUCLEO_F767ZI_SPI_TEST) -# if defined(CONFIG_STM32F7_SPI1) -struct spi_dev_s *spi1; -# endif -# if defined(CONFIG_STM32F7_SPI2) -struct spi_dev_s *spi2; -# endif -# if defined(CONFIG_STM32F7_SPI3) -struct spi_dev_s *spi3; -# endif -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -430,69 +376,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ - -#if defined(CONFIG_NUCLEO_F767ZI_SPI_TEST) -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI- */ - - uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE; - -#if defined(CONFIG_NUCLEO_F767ZI_SPI1_TEST) - spi1 = stm32_spibus_initialize(1); - - if (!spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to NUCLEO_F767ZI_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_FREQ); - SPI_SETBITS(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_BITS); - SPI_SETMODE(spi1, CONFIG_NUCLEO_F767ZI_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, - nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F767ZI_SPI2_TEST) - spi2 = stm32_spibus_initialize(2); - - if (!spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to NUCLEO_F767ZI_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_FREQ); - SPI_SETBITS(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_BITS); - SPI_SETMODE(spi2, CONFIG_NUCLEO_F767ZI_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, - nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_F767ZI_SPI3_TEST) - spi3 = stm32_spibus_initialize(3); - - if (!spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to NUCLEO_F767ZI_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_FREQ); - SPI_SETBITS(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_BITS); - SPI_SETMODE(spi3, CONFIG_NUCLEO_F767ZI_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, - nitems(CONFIG_NUCLEO_F767ZI_SPI_TEST_MESSAGE)); -#endif - - return OK; -} -#endif /* NUCLEO_F767ZI_SPI_TEST */ #endif /* defined(CONFIG_SPI) */
