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The following commit(s) were added to refs/heads/master by this push:
new ed8bfdd26a arch/arm64/imx9: Reset rx fifo in mode change
ed8bfdd26a is described below
commit ed8bfdd26a373b5af65fec880542599bdea1685b
Author: Jouni Ukkonen <[email protected]>
AuthorDate: Thu Nov 7 10:13:45 2024 +0200
arch/arm64/imx9: Reset rx fifo in mode change
instead of looping just reset rxfifo
Signed-off-by: Jouni Ukkonen <[email protected]>
---
arch/arm64/src/imx9/imx9_lpspi.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/src/imx9/imx9_lpspi.c b/arch/arm64/src/imx9/imx9_lpspi.c
index 610276a5f8..f78ddc51a6 100644
--- a/arch/arm64/src/imx9/imx9_lpspi.c
+++ b/arch/arm64/src/imx9/imx9_lpspi.c
@@ -1021,13 +1021,10 @@ static void imx9_lpspi_setmode(struct spi_dev_s *dev,
enum spi_mode_e mode)
imx9_lpspi_modifytcr(priv, clrbits, setbits);
- while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_RSR_OFFSET) &
- LPSPI_RSR_RXEMPTY) != LPSPI_RSR_RXEMPTY)
- {
- /* Flush SPI read FIFO */
+ /* Reset SPI read FIFO */
- imx9_lpspi_getreg32(priv, IMX9_LPSPI_RSR_OFFSET);
- }
+ imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0,
+ LPSPI_CR_RRF);
/* Save the mode so that subsequent re-configurations will be faster */
