pussuw opened a new pull request, #14967: URL: https://github.com/apache/nuttx/pull/14967
## Summary From the RISV-V Privileged Spec v1.10 (3.1.14 MIP/MIE): Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in mip are writable through this CSR address; the remaining bits are read-only. Thus, it is futile to write to the M-mode status bit via the CSR, only access via RISCV_IPI is valid. ## Impact RISC-V SMP only. ## Testing rv-virt:smp64 rv-virt:smp rv-virt:ksmp64 -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
