jlaitine opened a new pull request, #15140: URL: https://github.com/apache/nuttx/pull/15140
## Summary CoreSPI is a Microchip IP block, which can be instantiated on the FPGA inside MPFS SoC. This PR introduces two patches: 1) A simple bugfix for race condition in case of SPI timeout, resetting the signalling semaphore which may have been posted twice 2) Adding support for more SPI frame lengths: The CoreSPI has got a fixed frame length in bits, which is deceded at the time when the IP is instantiated on the FPGA. This poses a problem when the SPI transfer frame length can't be set during runtime. In particular, I need to be able to support both 8-bit and 16-bit transfers on the same SPI block, for two different types of IMU sensors. The problem can be circumvented by supporting SPI word lengths which are even multiples of the native frame length, by just writing multiple frames for each word. ## Impact This adds support for 16, 24 etc. bit widths for CoreSPI block configured for 8-bit frames. This adds support for more devices for MPFS platform when using 8-bit CoreSPI on the FPGA. It doesn't change the existing functionality. ## Testing Tested on custom MPFS board, running PX4, with different IMUs connected, using 8-bit and 16-bit SPI frames. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
