xiaoxiang781216 commented on code in PR #15821:
URL: https://github.com/apache/nuttx/pull/15821#discussion_r1965542094
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arch/xtensa/Kconfig:
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@@ -172,6 +172,10 @@ config XTENSA_DCACHE_LOCK
---help---
Enable Xtensa D-Cache lock & unlock feature
+config XTENSA_PERCPU_TCB_IN_MISC0
Review Comment:
> Sorry, @xiaoxiang781216 , I didn't see this answer.
>
> Just as a complement to my comment ([#15821
(comment)](https://github.com/apache/nuttx/pull/15821#issuecomment-2672365187)),
although it was tested with "with several chips from the different vendors",
these chips are not supported by NuttX (officially, NuttX supports only ESP32,
ESP32-S2 and ESP32-S3. Custom xtensa-based chips are possible, but they weren't
integrated to the tree).
>
please see https://github.com/apache/nuttx/pull/15821#issue-2847581269:
```
ostest passed on these config: esp32s3-devkit:smp, esp32s3-devkit:tickless,
esp32s2-saola-1:ostest,
with XTENSA_PERCPU_TCB_IN_MISC0 on and off (totally 6 combinations).
This feature does not work with esp32-devkitc:smp plus
XTENSA_PERCPU_TCB_IN_MISC0 on, ostest fails at signal handler test.
```
@chirping78 already test the change with esp32, esp32s3 and esp32s2, only
esp32 doesn't work.
> Furthermore, ESP32 longevity is 15 years from 2016 (EOL is expected to be
in 2031) (https://www.espressif.com/en/products/longevity-commitment), so it
isn't an "old" chip that is going to be deprecated soon. Its code base (which
is common for all xtensa devices) is not actively maintained by Espressif (it
was first developed by Greg), so leaving it behind because "it fails" without a
proper explanation doesn't make sense to me.
If the same code work with esp32s2 and esp32s3, but not esp32. The best
explanation should come from Espressif staff, the volunteer doesn't have enough
internal information and help to understand the difference around these chips.
The change is minor and weill commented, so could you give me a proper
explanation? esp32 maintainter.
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