bkempers opened a new issue, #15909:
URL: https://github.com/apache/nuttx/issues/15909
### Description
Hello all, I hope that this post is in the correct place. I'm coming to ask
for some clarification and help, I'm attempting to fix CMD24 timeout issues our
system is having with STM32H7 interfacing with a Kingston MW28. This has led me
down a rabbit hole trying to chase solutions in attempts to fix this.
During my attempts to resolve these timeout issues (would rather not just
increase DTIMER and WDATADELAY as doesn't seem to fix root issue of problem),
I've tried changing various configurations within the driver and chip itself.
I have attempted sending CMD6 SWITCH to alter the configuration of the card:
changing bus width to 4-bit mode, enabling enhanced attribute within
PARTITIONS_ATTRIBUTE, changing . However I have noticed that When I send any
CMD6 I have the resulting register values set:
```
//send cmd6
stm32_sendcmd: cmd: 00000446 arg: 039c0100 regval: 00001146 enabled irq:
0000812a
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000200
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 000001c0
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000180
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000140
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000100
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 000000c0
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000080
stm32_sdmmc_interrupt: recvfifo data STA 00009000 & DCOUNT 00000040
stm32_sdmmc_interrupt: ERROR: Data block CRC failure, remaining: 0
stm32_waitresponse: sta: 00081000 irq: 0000812a dctrl: 00000892 dcount
00000200 dlen 00000200
stm32_recvshortcrc: RECVR1 sta: 00000000 irq: 00000000 dctrl: 00000892
dcount 00000000 dlen 00000200
stm32_recvshortcrc: R1 response 00000800
```
The resulting DCOUNT and STA registers seem to suggest that there is data
waiting to be read in from our SDMMC driver. Only after configuring and setting
up the receive setup prior to sending the CMD6, then reading the resulting data
into our receive buffer, does the stm32_sdmmc.c driver becomes inactive and
allows for further commands to be sent (i.e. CMD13 SEND_STATUS).
It seems like `master` branch of patches has the option to send CMD6
BUS_WIDTH change toward the end of the initialization phase within
`mmcsd_sdio.c`, but doesn't handle the resulting RX FIFO buffer? I could be
wrong or have some weird configuration but if anyone has some insight it would
be greatly appreciated!
### Verification
- [x] I have verified before submitting the report.
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