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commit 51a75e622f16fc38e91a381464e80e4b05fce4a6
Author: Martin Vajnar <martin.vaj...@gmail.com>
AuthorDate: Sun Apr 27 14:19:55 2025 +0200
esp32[c6|h2|s3|s2]: Fix assignment of Edge/Level GPIO pins in PCNT
---
boards/risc-v/esp32c6/common/src/esp_board_pcnt.c | 4 ++--
boards/risc-v/esp32h2/common/src/esp_board_pcnt.c | 4 ++--
boards/xtensa/esp32/common/src/esp32_board_pcnt.c | 4 ++--
boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c | 4 ++--
boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
b/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
index 12beaec211..81e3938fd9 100644
--- a/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
+++ b/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
@@ -200,8 +200,8 @@ int board_pcnt_initialize(void)
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
- chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
- chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
diff --git a/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
b/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
index 1df1dcddfe..a0d31a9a5f 100644
--- a/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
+++ b/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
@@ -200,8 +200,8 @@ int board_pcnt_initialize(void)
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
- chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
- chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
diff --git a/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
b/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
index 6e53bd3212..722db97139 100644
--- a/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
+++ b/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
@@ -199,8 +199,8 @@ int board_pcnt_initialize(void)
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
- chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
- chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
b/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
index 3b2e970578..5629f9c899 100644
--- a/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
+++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
@@ -199,8 +199,8 @@ int board_pcnt_initialize(void)
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
- chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
- chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
b/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
index 01d0137746..916b23a06a 100644
--- a/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
+++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
@@ -199,8 +199,8 @@ int board_pcnt_initialize(void)
chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
#endif
- chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
- chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
+ chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
#ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
glitch_threshold = 0;
#else
