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new 7104a51411 arch/arm/imxrt: rt117x fix TCM/OCRAM ECC backdoor access
7104a51411 is described below
commit 7104a51411426c2e2979e4ab7c6c9c242fb11b4c
Author: Peter van der Perk <peter.vanderp...@nxp.com>
AuthorDate: Thu May 29 17:08:41 2025 +0200
arch/arm/imxrt: rt117x fix TCM/OCRAM ECC backdoor access
FlexRAM peripheral was incorrectly clocked and turned during
M7 sleep. This patch fixes clock setting and ensure that clock
stays on during M7 for backdoor access from for example eDMA
---
arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h | 4 ++++
arch/arm/src/imxrt/imxrt_clockconfig_ver2.c | 10 +++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h
b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h
index 64c3f270ae..1c81e396f6 100644
--- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_iomuxc.h
@@ -2397,6 +2397,10 @@
# define GPR_GPR16_FLEXRAM_BANK_CFG_SEL_FUSE (0 << 2) /* Use fuse
value to configure */
# define GPR_GPR16_FLEXRAM_BANK_CFG_SEL_REG (1 << 2) /* Use
FLEXRAM_BANK_CFG to configure */
+#define GPR_GPR16_CM7_FORCE_HCLK (1 << 3) /* Bit 3: Force FlexRAM
AHB clock during CM7 sleep (CM7_FORCE_HCLK) */
+# define GPR_GPR16_CM7_FORCE_HCLK_GATED (0 << 3) /* When CM7 is
sleeping and TCM is not accessible */
+# define GPR_GPR16_CM7_FORCE_HCLK_ENABLED (1 << 3) /* When CM7 is
sleeping and TCM is accessible */
+
/* Bit 4: Reserved */
#define GPR_GPR16_M7_GPC_SLEEP_SEL (1 << 5) /* Bit 5: CM7 sleep
request selection (M7_GPC_SLEEP_SEL) */
diff --git a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c
b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c
index e1fea76fa2..274783c939 100644
--- a/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c
+++ b/arch/arm/src/imxrt/imxrt_clockconfig_ver2.c
@@ -130,8 +130,16 @@ static void imxrt_oscsetup(void)
/* FlexRAM AXI CLK ROOT */
- putreg32(CCM_CG_CTRL_RSTDIV(1) | CCM_CG_CTRL_DIV0(1),
+ putreg32(CCM_CG_CTRL_RSTDIV(3) | CCM_CG_CTRL_DIV0(3),
IMXRT_CCM_CG_CTRL(0));
+
+ /* Keep TCM clock running during M7 sleep
+ * needed for DMA to read/write from TCM or OCRAM-M7 FlexRAM ECC
+ */
+
+ reg = getreg32(IMXRT_IOMUXC_GPR_GPR16);
+ putreg32(reg | GPR_GPR16_CM7_FORCE_HCLK_ENABLED,
+ IMXRT_IOMUXC_GPR_GPR16);
}
/****************************************************************************
