shtirlic commented on PR #16424:
URL: https://github.com/apache/nuttx/pull/16424#issuecomment-3173751275

   @cederom there are some pages in rp2350 datasheet `5.1.20. Automatic 
Architecture Switching` and `3.9. Arm/RISC-V Architecture Switching`  and for 
my board as I remember I set the ARCHSEL OTP register with optiion 4.
   ```
   1. If CRIT0_ARM_DISABLE is set, only RISC-V is allowed.
   2. Else if CRIT0_RISCV_DISABLE is set, only Arm is allowed.
   3. Else if CRIT1_SECURE_BOOT_ENABLE is set, only Arm is allowed.
   4. Else if CRIT1_BOOT_ARCH is set, both architectures are permitted, and the 
default is RISC-V.
   5. If none of the above flags are set, both architectures are permitted, and 
the default is Arm.
   No CRIT1 flags are set by default, so on devices where both architectures 
are available, the default is Arm. To change the
   default architecture to RISC-V, set the CRIT1_BOOT_ARCH flag to 1.
   ```
   my OTP looks like this, see the BOOT_ARCH bit set to 1
   ```
   luksdev> picotool otp get OTP_DATA_CRIT1
   ROW 0x0040: OTP_DATA_CRIT1
           "Page 1 critical boot flags (RBIT-8)"
   
       VALUE 0x000008
   
       field GLITCH_DETECTOR_SENS (bits 5-6) = 0
           "Increase the sensitivity of the glitch detectors from their 
default."
       field GLITCH_DETECTOR_ENABLE (bit 4) = 0
           "Arm the glitch detectors to reset the system if an abnormal 
clock/power event is observed."
       field BOOT_ARCH (bit 3) = 1
           "Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if 
ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set."
       field DEBUG_DISABLE (bit 2) = 0
           "Disable all debug access"
       field SECURE_DEBUG_DISABLE (bit 1) = 0
           "Disable Secure debug access"
       field SECURE_BOOT_ENABLE (bit 0) = 0
           "Enable boot signature enforcement, and permanently disable the 
RISC-V cores."
   ```
   and `picotool info -a`
   
   ```
   Device Information
    type:                   RP2350
    revision:               A2
    package:                QFN60
    chipid:                 0x87485d01e86f300a
    flash devinfo:          0x0c00
    current cpu:            RISC-V
    available cpus:         ARM, RISC-V
    default cpu:            RISC-V
    secure boot:            0
    debug enable:           1
    secure debug enable:    1
    boot_random:            c403df64:02852428:7ac04dce:1d37e89f
    boot type:              bootsel
    last booted partition:  none
    diagnostic source:      slot 0
    last boot diagnostics:  0x00000000
    reboot param 0:         0x00000000
    reboot param 1:         0x00000000
    rom gitrev:             0x312e22fa
    flash size:             4096K
   ```
   
   
   
   
   


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