(nuttx) 02/02: arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reserved IO area in protected build

[acassis]

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commit 85f6f4bca29b2d9c7554250591fbc60bde8a1139
Author: Jukka Laitinen <juk...@ssrc.tii.ae>
AuthorDate: Thu Feb 9 20:53:42 2023 +0400

    arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reserved IO 
area in protected build
    
    Signed-off-by: Jukka Laitinen <juk...@ssrc.tii.ae>
---
 arch/risc-v/src/mpfs/hardware/mpfs_clint.h | 6 ++++++
 arch/risc-v/src/mpfs/mpfs_userspace.c      | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_clint.h 
b/arch/risc-v/src/mpfs/hardware/mpfs_clint.h
index 1e963d7a4fb..ea2a5ae151f 100644
--- a/arch/risc-v/src/mpfs/hardware/mpfs_clint.h
+++ b/arch/risc-v/src/mpfs/hardware/mpfs_clint.h
@@ -23,6 +23,12 @@
 #ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H
 #define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H
 
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "mpfs_memorymap.h"
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
diff --git a/arch/risc-v/src/mpfs/mpfs_userspace.c 
b/arch/risc-v/src/mpfs/mpfs_userspace.c
index 8bf62b1d6ea..ebe597d65b4 100644
--- a/arch/risc-v/src/mpfs/mpfs_userspace.c
+++ b/arch/risc-v/src/mpfs/mpfs_userspace.c
@@ -33,6 +33,7 @@
 #include <nuttx/userspace.h>
 
 #include <arch/board/board_memorymap.h>
+#include "hardware/mpfs_clint.h"
 
 #include "mpfs_userspace.h"
 #include "riscv_internal.h"
@@ -250,6 +251,11 @@ static void configure_mmu(void)
   map_region(UFLASH_START, UFLASH_START, UFLASH_SIZE, MMU_UTEXT_FLAGS);
   map_region(USRAM_START, USRAM_START, USRAM_SIZE, MMU_UDATA_FLAGS);
 
+  /* Map the MTIME counter to the start of USR IO region */
+
+  map_region(MPFS_CLINT_MTIME & (~RV_MMU_PAGE_MASK), USRIO_START,
+             RV_MMU_PAGE_SIZE, PTE_R | PTE_U | PTE_G);
+
   /* Connect the L1 and L2 page tables */
 
   mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBASE, UFLASH_START, PTE_G);