jlaitine opened a new pull request, #17173: URL: https://github.com/apache/nuttx/pull/17173
## Summary Microchip PolarFire SoC has got 5 risc-v harts, one E51 monitor core and 4 U54 application cores. This PR enables caches also on E51 monitor core. This differs from U54, there is a vendor specific CSR register write needed to enable the instruction and data caches at boot. Current board files already correctly configure L2 cache lanes also for E51 core, but actually also L2 is also not enabled at the moment, because L1 needs to be enabled for that as well. This was found when we noticed that certain operations which we do on E51 in DDR memory were a lot slower than expected. ## Impact Doesn't really impact the current board configurations since they use u-boot on e51. When running on E51, this enables the caches. ## Testing I have tested on a custom board configuration that - Caches are enabled on E51 after this change (by instrumenting code, printing out CSR register values after boot) - This doesn't impact the operation on U54 cores - All SW works properly on all harts of the MPFS Logs are not provided due to this change doesn't really provide any logs as such, and there is no upstream board configuration which uses E51. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
