Re: [PR] arch/xtensa/esp32s3: expose UART RX FIFO controls [nuttx]

Sat, 18 Oct 2025 00:27:32 -0700 


thiagofinelon commented on PR #17202:
URL: https://github.com/apache/nuttx/pull/17202#issuecomment-3408167539

   > Im using this patch in a esp32s3 based hw, my application runs pppd on a 
lpwa modem. This is the log analyzer screenshot:
   > 
   > <img alt="image" width="1282" height="1029" 
src="https://private-user-images.githubusercontent.com/39820881/501707178-482ad549-84b3-4aac-bda6-354abe124311.png?jwt=eyJ0eXAiOiJKV1QiLCJhbGciOiJIUzI1NiJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NjA1NjA0MTMsIm5iZiI6MTc2MDU2MDExMywicGF0aCI6Ii8zOTgyMDg4MS81MDE3MDcxNzgtNDgyYWQ1NDktODRiMy00YWFjLWJkYTYtMzU0YWJlMTI0MzExLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNTEwMTUlMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjUxMDE1VDIwMjgzM1omWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWFmMTg5YTdmMzcxZjE1YjgwYmQ0ZGNhNGFlNWI0YTYxMGFkMzFhNjlkZGM5YTkxMGM0YTJlYjRiN2U3ZGYxNmEmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0In0.1rlnGkmXm-SUN6Ge5klOr65SHJIx1_1fP7I4t6vPS8I";>
   > In this application Im using:
   > 
   > * UART2 with 115200 baudrate;
   > * rx fifo threshold = 8;
   > * rx fifo timeout = 10.
   
   <img width="889" height="946" alt="image" 
src="https://github.com/user-attachments/assets/fd7710a2-35c6-4827-9d23-d12e84b685e1";
 />
   
   Heres a chat connect sequence, showing at comands 


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