adriendesp opened a new pull request, #17228: URL: https://github.com/apache/nuttx/pull/17228
## Summary On XMC4, the USIC peripheral has a FIFO buffer. In UART mode, the FIFO is used to store data at reception. Until now, the FIFO size was set by user with XMC4_USICx_CHANy_RX_BUFFER_SIZE. And an interrupt was geenerated when the fifo was full. At higher baudrate (ex: 921600), I observed that the interrupt routine wouldn't empty the buffer before the reception of the next byte (too much time spent in the ISR), thus leading to missed bytes. This PR add the possibility to trigger an interrupt before the buffer is full, the trigger level is set by user in menconfig between 1 and XMC4_USICx_CHANy_RX_BUFFER_SIZE. ## Impact By default the value is set to XMC4_USICx_CHANy_RX_BUFFER_SIZE, as it is today so no impact on existing boards. ## Testing Tested on a custom XMC4800 board. USIC0_CHAN0 and USIC0_CHAN1 set as UART. Communication with both UART still working. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
