linguini1 commented on code in PR #17229: URL: https://github.com/apache/nuttx/pull/17229#discussion_r2452839652
########## arch/arm/src/am67/am67_irq.c: ########## @@ -0,0 +1,379 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <assert.h> + +#include "arm_internal.h" +#include "irq/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INTR_MAX_INTERRUPTS (512u) +#define INTR_MAX_PRIORITY (16u) +#define INTRC_BASE_ADDR 0x2fff0000u + +#define VIM_BIT_POS(j) ( (j) & 0x1fu ) +#define VIM_IRQVEC (0x18u) +#define VIM_ACTIRQ (0x20u) +#define VIM_RAW(j) (0x400u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_STS(j) (0x404u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_EN(j) (0x408u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_DIS(j) (0x40cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_MAP(j) (0x418u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_TYPE(j) (0x41cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_PRI(j) (0x1000u + ((j) * 0x4u)) +#define VIM_INT_VEC(j) (0x2000u + ((j) * 0x4u)) + +#define INTR_SUCCESS ((int32_t)0) +#define INTR_FAILURE ((int32_t)-1) +#define INTR_TIMEOUT ((int32_t)-2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num); +static void intr_ack_irq(uint32_t int_num); +static void intr_clear_irq(uint32_t int_num); +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority); +static uint32_t intr_get_irq_vec_addr(void); +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr); + +static void utils_data_and_instruction_barrier(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intr_get_irq + * + * Description: + * Return the interrupt status corresponding to the given int_num. + * + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num) +{ + volatile uint32_t *addr; + int32_t status = INTR_FAILURE; + uint32_t value; + + *int_num = 0; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_ACTIRQ); + value = *addr; + + if ((value & 0x80000000u) != 0U) + { + *int_num = (value & (INTR_MAX_INTERRUPTS - 1U)); + status = INTR_SUCCESS; + } + + return status; +} + +/**************************************************************************** + * Name: intr_ack_irq + * + * Description: + * Acknowledge a specific interrupt number by writing to the interrupt + * controller's IRQVEC register. + * + ****************************************************************************/ + +static void intr_ack_irq(uint32_t int_num) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_IRQVEC); + *addr = int_num; +} + +/**************************************************************************** + * Name: intr_clear_irq + * + * Description: + * Clear a specific interrupt by setting the corresponding bit in the + * interrupt status register. + * + ****************************************************************************/ + +static void intr_clear_irq(uint32_t int_num) +{ + volatile uint32_t *addr; + uint32_t bit_pos; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_STS(int_num)); + bit_pos = VIM_BIT_POS(int_num); + + *addr = (0x1u << bit_pos); +} + +/**************************************************************************** + * Name: intr_set_irq_pri + * + * Description: + * Set the priority level (0–15) for a specified interrupt. + * + ****************************************************************************/ + +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_INT_PRI(int_num)); + + *addr = (priority & 0xfu); +} + +/**************************************************************************** + * Name: intr_get_irq_vec_addr + * + * Description: + * Get the interrupt vector address for a specific interrupt number from + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static uint32_t intr_get_irq_vec_addr(void) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_IRQVEC); + + return *addr; +} + +/**************************************************************************** + * Name: intr_set_irq_vec_addr + * + * Description: + * Set the interrupt vector address for a specific interrupt number into + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_INT_VEC(int_num)); + + *addr = ((uint32_t)vec_addr & 0xfffffffcu); +} + +/**************************************************************************** + * Name: utils_data_and_instruction_barrier + * + * Description: + * Enforces CPU memory ordering by executing an Instruction Synchronization + * Barrier (ISB) followed by a Data Synchronization Barrier (DSB), + * ensuring all previous instructions complete and memory accesses are + * synchronized before continuing execution. + * + ****************************************************************************/ + +static void utils_data_and_instruction_barrier(void) Review Comment: I think there might be an architecture implementation for this for all ARM chips, you should re-use that instead. I think `UP_DMB` is for data memory, there is probably something similar for other barriers. ########## arch/arm/src/am67/am67_timer.c: ########## @@ -0,0 +1,494 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/timers/arch_alarm.h> +#include <fcntl.h> +#include <stdint.h> +#include <time.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TIMER0_CLOCK_SRC_MUX_ADDR (0x1081b0u) +#define TIMER0_CLOCK_SRC_HFOSC0_CLKOUT (0x0u) +#define TIMER0_BASE_ADDR (0x2400000u) + +#define AM67_DMTIMER1_1MS_TIMER0_VADDR 0x2400000 +#define AM67_DMTMR1MS_TIDR_OFFSET 0x0000 /* Identification Register Section */ +#define AM67_DMTMR1MS_TIOCP_CFG_OFFSET 0x0010 /* 1ms Timer OCP Configuration Register Section */ +#define AM67_DMTMR1MS_IRQ_EOI_OFFSET 0x0020 /* 1ms Timer IRQ Wakeup Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_RAW_OFFSET 0x0024 /* 1ms Timer IRQ Status Register */ +#define AM67_DMTMR1MS_IRQSTATUS_OFFSET 0x0028 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_SET_OFFSET 0x002c /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_CLR_OFFSET 0x0030 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQWAKEEN_OFFSET 0x0034 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_TCLR_OFFSET 0x0038 /* 1ms Timer Control Register */ +#define AM67_DMTMR1MS_TCRR_OFFSET 0x003c /* 1ms Timer Counter Register */ +#define AM67_DMTMR1MS_TLDR_OFFSET 0x0040 /* 1ms Timer Load Register */ +#define AM67_DMTMR1MS_TTGR_OFFSET 0x0044 /* 1ms Timer Trigger Register */ +#define AM67_DMTMR1MS_TWPS_OFFSET 0x0048 /* 1ms Timer Write Posting Bits Register */ +#define AM67_DMTMR1MS_TMAR_OFFSET 0x004c /* 1ms Timer Match Register */ +#define AM67_DMTMR1MS_TCAR1_OFFSET 0x0050 /* 1ms Timer Capture 1 Register */ +#define AM67_DMTMR1MS_TSICR_OFFSET 0x0054 /* 1ms Timer Synchronous Interface Control Register */ +#define AM67_DMTMR1MS_TCAR2_OFFSET 0x0058 /* 1ms Timer Capture 2 Register */ +#define AM67_DMTMR1MS_TPIR_OFFSET 0x005c /* 1ms Timer Positive Increment Register */ +#define AM67_DMTMR1MS_TNIR_OFFSET 0x0060 /* 1ms Timer Negative Increment Register */ +#define AM67_DMTMR1MS_TCVR_OFFSET 0x0064 /* 1ms Timer Counter Value Register */ +#define AM67_DMTMR1MS_TOCR_OFFSET 0x0068 /* 1ms Timer Overflow Counter Register */ +#define AM67_DMTMR1MS_TOWR_OFFSET 0x006c /* 1ms Timer Overflow Interrupts Register */ Review Comment: Would suggest surrounding all these values in parentheses to be safe, avoids unexpected errors if these macros get used improperly in the future. ########## arch/arm/src/am67/am67_mpuinit.c: ########## @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_mpuinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/userspace.h> +#include <arch/barriers.h> +#include <assert.h> +#include <sys/param.h> + +#include "am67_mpuinit.h" +#include "mpu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_mpu_reset + * + * Description: + * Reset all MPU regions by disabling each region. + * + ****************************************************************************/ + +void am67_mpu_reset(void) +{ + for (int i = 0; i < NUM_OF_REGION; i++) + { + mpu_set_region_zero(i); + } +} + +/**************************************************************************** + * Name: am67_mpu_init + * + * Description: + * Initialize the MPU by disabling it, resetting all regions, configuring + * specific memory regions, and then re-enabling the MPU. + * + ****************************************************************************/ + +void am67_mpu_init(void) +{ + mpu_control(false); + + am67_mpu_disable_br(); + + am67_mpu_reset(); + + am67_register_region(ARM67_REGISTER_START_ADDR, ARM67_REGISTER_SIZE); + am67_tcma_region(ARM67_TCMA_START_ADDR, ARM67_TCMA_SIZE); + am67_tcmb_region(ARM67_TCMB_START_ADDR, ARM67_TCMB_SIZE); + am67_mcu_msram_region(ARM67_MCU_MSRAM_START_ADDR, ARM67_MCU_MSRAM_SIZE); + am67_ddr_region(ARM67_DDR_START_ADDR, ARM67_DDR_SIZE); + + mpu_control(true); + + return; Review Comment: Unnecessary line. ########## arch/arm/src/am67/am67_pinmux.h: ########## @@ -0,0 +1,316 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_AM67_PINMUX_H +#define __ARCH_ARM_SRC_AM67_AM67_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CSL_PADCFG_CTRL0_CFG0_BASE (0xf0000ul) +#define CSL_PADCFG_CTRL0_CFG0_SIZE (0x8000ul) + +#define CSL_MCU_PADCFG_CTRL0_CFG0_BASE (0x4080000ul) +#define CSL_MCU_PADCFG_CTRL0_CFG0_SIZE (0x8000ul) + +#define PADCFG_PMUX_OFFSET (0x4000u) + +#define CSL_MAIN_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008) +#define CSL_MAIN_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008) +#define CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET (0x1008) +#define CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET (0x5008) + +#define KICK_LOCK_VAL (0x00000000u) +#define KICK0_UNLOCK_VAL (0x68ef3490u) +#define KICK1_UNLOCK_VAL (0xd172bc5au) + +#define PINMUX_END (-1) + +#define PIN_MODE(mode) ((uint32_t) mode) +#define PIN_PULL_DISABLE (((uint32_t) 0x1u) << 16u) +#define PIN_PULL_DIRECTION (((uint32_t) 0x1u) << 17u) +#define PIN_INPUT_ENABLE (((uint32_t) 0x1u) << 18u) +#define PIN_OUTPUT_DISABLE (((uint32_t) 0x1u) << 21u) +#define PIN_WAKEUP_ENABLE (((uint32_t) 0x1u) << 29u) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum pinmux_main_offsets_e +{ + PIN_MMC1_DAT1 = 0x022c, + PIN_MMC1_DAT0 = 0x0230, + PIN_EXT_REFCLK1 = 0x01f0, + PIN_MMC1_DAT3 = 0x0224, + PIN_MMC1_DAT2 = 0x0228, + PIN_VOUT0_VSYNC = 0x0100, + PIN_VOUT0_HSYNC = 0x00f8, + PIN_VOUT0_PCLK = 0x0104, + PIN_VOUT0_DE = 0x00fc, + PIN_VOUT0_DATA0 = 0x00b8, + PIN_VOUT0_DATA1 = 0x00bc, + PIN_VOUT0_DATA2 = 0x00c0, + PIN_VOUT0_DATA3 = 0x00c4, + PIN_VOUT0_DATA4 = 0x00c8, + PIN_VOUT0_DATA5 = 0x00cc, + PIN_VOUT0_DATA6 = 0x00d0, + PIN_VOUT0_DATA7 = 0x00d4, + PIN_VOUT0_DATA8 = 0x00d8, + PIN_VOUT0_DATA9 = 0x00dc, + PIN_VOUT0_DATA10 = 0x00e0, + PIN_VOUT0_DATA11 = 0x00e4, + PIN_VOUT0_DATA12 = 0x00e8, + PIN_VOUT0_DATA13 = 0x00ec, + PIN_VOUT0_DATA14 = 0x00f0, + PIN_VOUT0_DATA15 = 0x00f4, + PIN_GPMC0_AD8 = 0x005c, + PIN_GPMC0_AD9 = 0x0060, + PIN_GPMC0_AD10 = 0x0064, + PIN_GPMC0_AD11 = 0x0068, + PIN_GPMC0_AD12 = 0x006c, + PIN_GPMC0_AD13 = 0x0070, + PIN_GPMC0_AD14 = 0x0074, + PIN_GPMC0_AD15 = 0x0078, + PIN_GPMC0_WAIT1 = 0x009c, + PIN_SPI0_CS1 = 0x01bb, + PIN_UART0_TXD = 0x01cc, + PIN_UART0_RXD = 0x01c8, + PIN_SPI0_CS0 = 0x01b4, + PIN_MMC0_DAT3 = 0x0208, + PIN_I2C1_SCL = 0x01e8, + PIN_I2C1_SDA = 0x01ec, + PIN_MMC0_CLK = 0x0218, + PIN_MMC0_CMD = 0x0220, + PIN_SPI0_CLK = 0x01bc, + PIN_SPI0_D0 = 0x01c0, + PIN_I2C0_SCL = 0x01e0, + PIN_I2C0_SDA = 0x01e4, + PIN_SPI0_D1 = 0x01c4, + PIN_MMC0_DAT0 = 0x0214, + PIN_MMC0_DAT5 = 0x0200, + PIN_MCAN0_TX = 0x01d8, + PIN_MCAN0_RX = 0x01dc, + PIN_MCASP0_ACLKX = 0x01a4, + PIN_MCASP0_AFSX = 0x01a8, + PIN_MCASP0_ACLKR = 0x01b0, + PIN_MCASP0_AFSR = 0x01ac, + PIN_RGMII2_RD2 = 0x018c, + PIN_RGMII2_RD3 = 0x0190, + PIN_RGMII2_TD2 = 0x0174, + PIN_GPMC0_DIR = 0x00a4, + PIN_MCASP0_AXR3 = 0x0194, + PIN_MCASP0_AXR2 = 0x0198, + PIN_MCASP0_AXR0 = 0x01a0, + PIN_MCASP0_AXR1 = 0x019c, + PIN_GPMC0_CSN3 = 0x00b4, + PIN_GPMC0_WPN = 0x00a0, + PIN_GPMC0_AD0 = 0x003c, + PIN_GPMC0_AD1 = 0x0040, + PIN_GPMC0_AD2 = 0x0044, + PIN_GPMC0_AD3 = 0x0048, + PIN_GPMC0_AD4 = 0x004c, + PIN_GPMC0_AD5 = 0x0050, + PIN_GPMC0_AD6 = 0x0054, + PIN_GPMC0_AD7 = 0x0058, + PIN_GPMC0_WAIT0 = 0x0098, + PIN_GPMC0_BE1N = 0x0094, + PIN_GPMC0_CSN0 = 0x00a8, + PIN_GPMC0_CLK = 0x007c, + PIN_GPMC0_ADVN_ALE = 0x0084, + PIN_GPMC0_OEN_REN = 0x0088, + PIN_GPMC0_WEN = 0x008c, + PIN_GPMC0_BE0N_CLE = 0x0090, + PIN_UART0_CTSN = 0x01d0, + PIN_UART0_RTSN = 0x01d4, + PIN_GPMC0_CSN2 = 0x00b0, + PIN_MMC0_DAT6 = 0x01fc, + PIN_MMC0_DAT7 = 0x01f8, + PIN_OSPI0_D6 = 0x0024, + PIN_OSPI0_D7 = 0x0028, + PIN_OSPI0_D5 = 0x0020, + PIN_RGMII2_TD3 = 0x0178, + PIN_RGMII2_TX_CTL = 0x0164, + PIN_MDIO0_MDC = 0x0160, + PIN_MDIO0_MDIO = 0x015c, + PIN_MMC0_DAT1 = 0x0210, + PIN_MMC0_DAT2 = 0x020c, + PIN_MMC0_DAT4 = 0x0204, + PIN_MMC1_CMD = 0x023c, + PIN_MMC1_CLK = 0x0234, + PIN_MMC1_SDCD = 0x0240, + PIN_MMC1_SDWP = 0x0244, + PIN_MMC2_CMD = 0x0120, + PIN_MMC2_CLK = 0x0118, + PIN_MMC2_DAT0 = 0x0114, + PIN_MMC2_DAT1 = 0x0110, + PIN_MMC2_DAT2 = 0x010c, + PIN_MMC2_DAT3 = 0x0108, + PIN_MMC2_SDCD = 0x0124, + PIN_MMC2_SDWP = 0x0128, + PIN_OLDI0_A0N = 0x0260, + PIN_OLDI0_A0P = 0x025c, + PIN_OLDI0_A1N = 0x0268, + PIN_OLDI0_A1P = 0x0264, + PIN_OLDI0_A2N = 0x0270, + PIN_OLDI0_A2P = 0x026c, + PIN_OLDI0_A3N = 0x0278, + PIN_OLDI0_A3P = 0x0274, + PIN_OLDI0_A4N = 0x0280, + PIN_OLDI0_A4P = 0x027c, + PIN_OLDI0_A5N = 0x0288, + PIN_OLDI0_A5P = 0x0284, + PIN_OLDI0_A6N = 0x0290, + PIN_OLDI0_A6P = 0x028c, + PIN_OLDI0_A7N = 0x0298, + PIN_OLDI0_A7P = 0x0294, + PIN_OLDI0_CLK0N = 0x02a0, + PIN_OLDI0_CLK0P = 0x029c, + PIN_OLDI0_CLK1N = 0x02a8, + PIN_OLDI0_CLK1P = 0x02a4, + PIN_OSPI0_CLK = 0x0000, + PIN_OSPI0_CSN0 = 0x002c, + PIN_OSPI0_CSN1 = 0x0030, + PIN_OSPI0_CSN2 = 0x0034, + PIN_OSPI0_CSN3 = 0x0038, + PIN_OSPI0_D0 = 0x000c, + PIN_OSPI0_D1 = 0x0010, + PIN_OSPI0_D2 = 0x0014, + PIN_OSPI0_D3 = 0x0018, + PIN_OSPI0_D4 = 0x001c, + PIN_OSPI0_DQS = 0x0008, + PIN_RGMII1_RD0 = 0x014c, + PIN_RGMII1_RD1 = 0x0150, + PIN_RGMII1_RD2 = 0x0154, + PIN_RGMII1_RD3 = 0x0158, + PIN_RGMII1_RXC = 0x0148, + PIN_RGMII1_RX_CTL = 0x0144, + PIN_RGMII1_TD0 = 0x0134, + PIN_RGMII1_TD1 = 0x0138, + PIN_RGMII1_TD2 = 0x013c, + PIN_RGMII1_TD3 = 0x0140, + PIN_RGMII1_TXC = 0x0130, + PIN_RGMII1_TX_CTL = 0x012c, + PIN_RGMII2_RD0 = 0x0184, + PIN_RGMII2_RD1 = 0x0188, + PIN_RGMII2_RXC = 0x0180, + PIN_RGMII2_RX_CTL = 0x017c, + PIN_RGMII2_TD0 = 0x016c, + PIN_RGMII2_TD1 = 0x0170, + PIN_RGMII2_TXC = 0x0168, + PIN_EXTINTN = 0x01f4, + PIN_PORZ_OUT = 0x0250, + PIN_RESETSTATZ = 0x024c, + PIN_RESET_REQZ = 0x0248, + PIN_GPMC0_CSN1 = 0x00ac, + PIN_OSPI0_LBCLKO = 0x0004, + PIN_USB1_DRVVBUS = 0x0258, + PIN_USB0_DRVVBUS = 0x0254, + PIN_PCIE0_CLKREQN = 0x02ac, +}; + +enum pinmux_mcu_offsets_e +{ + PIN_EMU0 = 0x0078, + PIN_EMU1 = 0x007c, + PIN_TCK = 0x0064, + PIN_TDI = 0x006c, + PIN_TDO = 0x0070, + PIN_TMS = 0x0074, + PIN_TRSTN = 0x0068, + PIN_MCU_I2C0_SCL = 0x0044, + PIN_MCU_I2C0_SDA = 0x0048, + PIN_MCU_MCAN1_RX = 0x0040, + PIN_MCU_MCAN1_TX = 0x003c, + PIN_MCU_MCAN0_RX = 0x0038, + PIN_MCU_MCAN0_TX = 0x0034, + PIN_MCU_SPI0_CLK = 0x0008, + PIN_MCU_SPI0_CS0 = 0x0000, + PIN_MCU_SPI0_D0 = 0x000c, + PIN_MCU_SPI0_D1 = 0x0010, + PIN_WKUP_UART0_RTSN = 0x0030, + PIN_WKUP_UART0_CTSN = 0x002c, + PIN_MCU_UART0_CTSN = 0x001c, + PIN_MCU_UART0_RTSN = 0x0020, + PIN_MCU_ERRORN = 0x0060, + PIN_MCU_SPI0_CS1 = 0x0004, + PIN_MCU_PORZ = 0x0058, + PIN_MCU_RESETSTATZ = 0x005c, + PIN_MCU_RESETZ = 0x0054, + PIN_MCU_UART0_RXD = 0x0014, + PIN_MCU_UART0_TXD = 0x0018, + PIN_WKUP_I2C0_SCL = 0x004c, + PIN_WKUP_I2C0_SDA = 0x0050, + PIN_WKUP_CLKOUT0 = 0x0084, + PIN_PMIC_LPM_EN0 = 0x0080, + PIN_WKUP_UART0_RXD = 0x0024, + PIN_WKUP_UART0_TXD = 0x0028, +}; + +struct pinmux_conf_s +{ + int16_t offset; + uint32_t setting; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + Review Comment: If these sections don't exist, just omit them in your files. ########## arch/arm/src/am67/am67_timer.c: ########## @@ -0,0 +1,494 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/timers/arch_alarm.h> +#include <fcntl.h> +#include <stdint.h> +#include <time.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TIMER0_CLOCK_SRC_MUX_ADDR (0x1081b0u) +#define TIMER0_CLOCK_SRC_HFOSC0_CLKOUT (0x0u) +#define TIMER0_BASE_ADDR (0x2400000u) + +#define AM67_DMTIMER1_1MS_TIMER0_VADDR 0x2400000 +#define AM67_DMTMR1MS_TIDR_OFFSET 0x0000 /* Identification Register Section */ +#define AM67_DMTMR1MS_TIOCP_CFG_OFFSET 0x0010 /* 1ms Timer OCP Configuration Register Section */ +#define AM67_DMTMR1MS_IRQ_EOI_OFFSET 0x0020 /* 1ms Timer IRQ Wakeup Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_RAW_OFFSET 0x0024 /* 1ms Timer IRQ Status Register */ +#define AM67_DMTMR1MS_IRQSTATUS_OFFSET 0x0028 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_SET_OFFSET 0x002c /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_CLR_OFFSET 0x0030 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQWAKEEN_OFFSET 0x0034 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_TCLR_OFFSET 0x0038 /* 1ms Timer Control Register */ +#define AM67_DMTMR1MS_TCRR_OFFSET 0x003c /* 1ms Timer Counter Register */ +#define AM67_DMTMR1MS_TLDR_OFFSET 0x0040 /* 1ms Timer Load Register */ +#define AM67_DMTMR1MS_TTGR_OFFSET 0x0044 /* 1ms Timer Trigger Register */ +#define AM67_DMTMR1MS_TWPS_OFFSET 0x0048 /* 1ms Timer Write Posting Bits Register */ +#define AM67_DMTMR1MS_TMAR_OFFSET 0x004c /* 1ms Timer Match Register */ +#define AM67_DMTMR1MS_TCAR1_OFFSET 0x0050 /* 1ms Timer Capture 1 Register */ +#define AM67_DMTMR1MS_TSICR_OFFSET 0x0054 /* 1ms Timer Synchronous Interface Control Register */ +#define AM67_DMTMR1MS_TCAR2_OFFSET 0x0058 /* 1ms Timer Capture 2 Register */ +#define AM67_DMTMR1MS_TPIR_OFFSET 0x005c /* 1ms Timer Positive Increment Register */ +#define AM67_DMTMR1MS_TNIR_OFFSET 0x0060 /* 1ms Timer Negative Increment Register */ +#define AM67_DMTMR1MS_TCVR_OFFSET 0x0064 /* 1ms Timer Counter Value Register */ +#define AM67_DMTMR1MS_TOCR_OFFSET 0x0068 /* 1ms Timer Overflow Counter Register */ +#define AM67_DMTMR1MS_TOWR_OFFSET 0x006c /* 1ms Timer Overflow Interrupts Register */ + +#define TIMER_OVF_INT_SHIFT (0x1) +#define TIMER_IRQ_EOI (0x20u) +#define TIMER_IRQ_STATUS_RAW (0x24u) +#define TIMER_IRQ_STATUS (0x28u) +#define TIMER_IRQ_INT_ENABLE (0x2cu) +#define TIMER_IRQ_INT_DISABLE (0x30u) +#define TIMER_TCLR (0x38u) +#define TIMER_TCRR (0x3cu) +#define TIMER_TLDR (0x40u) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct timer_params_s +{ + /* Input pre-scaler divisor ro apply + * + * Must be power of 2 and between 1 and 256 for GP Timer. + * + * This field is valid only when underlying timer is DM Timer. + * + * This field is not valid when underlying timer is RTI Timer, + * set to 1 in this case. + */ + + uint32_t input_pre_scaler; + + /* Timer input clock in unit of Hz before pre-scaler + * + * System initialization must make any system level muxes, PLLs, + * power required to input this clock are setup properly. + * + * Make sure this value is not 0. + */ + + uint32_t input_clk_hz; + + /* Timer period in units of usecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_usec; + + /* Timer period in units of nsecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_nsec; + + /* 0: continuous mode of operation + * 1: oneshot mode of operation + * + * Not supported for RTI timer, always set to 0 in this case. + */ + + uint32_t oneshot_mode; + + /* 0: do not enable timer overflow interrupt + * 1: enable timer overflow interrupt + */ + + uint32_t enable_overflow_int; + + /* 0: do not enable DMA trigger from timer + * 1: enable DMA trigger from timer + */ + + uint32_t enable_dma_trigger; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr); +static void am67_timer_stop(uint32_t base_addr); +static uint32_t am67_timer_get_count(uint32_t base_addr); +static void am67_timer_clear_overflow_int(uint32_t base_addr); +static void am67_timer_params_init(struct timer_params_s *params); +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_timer_start + * + * Description: + * Start the timer by setting the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr) +{ + volatile uint32_t *addr = (uint32_t *)(base_addr + TIMER_TCLR); + + *addr |= (0x1u << 0); +} + +/**************************************************************************** + * Name: am67_timer_stop + * + * Description: + * Stop the timer by clearing the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_stop(uint32_t base_addr) +{ + volatile uint32_t *addr = (volatile uint32_t *)(base_addr + TIMER_TCLR); + + *addr &= ~(0x1u << 0); +} + +/**************************************************************************** + * Name: am67_timer_get_count + * + * Description: + * Read and return the current timer count value from the timer counter + * register. + * + ****************************************************************************/ + +static uint32_t am67_timer_get_count(uint32_t base_addr) +{ + volatile uint32_t *addr = (volatile uint32_t *)(base_addr + TIMER_TCRR); + + return *addr; +} + +/**************************************************************************** + * Name: am67_timer_clear_overflow_int + * + * Description: + * Clear the timer overflow interrupt by writing to the interrupt status + * register and verify the interrupt is cleared. + * + ****************************************************************************/ + +static void am67_timer_clear_overflow_int(uint32_t base_addr) +{ + volatile uint32_t *addr; + uint32_t value = (0x1u << TIMER_OVF_INT_SHIFT); + + /* Clear status for overflow interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_STATUS); + *addr = value; + + /* Read back and make sure interrupt was indeed cleared, + * if not clear it again. + */ + + if ((bool)(*addr & value) == true) + { + *addr = value; + } +} + +/**************************************************************************** + * Name: am67_timer_params_init + * + * Description: + * Initialize timer parameters with default values including prescaler, + * clock frequency, period, and operational mode settings. + * + ****************************************************************************/ + +static void am67_timer_params_init(struct timer_params_s *params) +{ + params->input_pre_scaler = 1; + params->input_clk_hz = 25 * 1000000; + params->period_in_usec = 10000; + params->period_in_nsec = 0; + params->oneshot_mode = 0; + params->enable_overflow_int = 1; + params->enable_dma_trigger = 0; +} + +/**************************************************************************** + * Name: am67_timer_setup + * + * Description: + * Configure timer parameters including period, mode, prescaler, and + * interrupts based on the provided timer parameters structure. + * + ****************************************************************************/ + +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params) +{ + volatile uint32_t *addr; + uint32_t ctrl_val; + uint32_t count_val; + uint32_t reload_val; + uint64_t time_in_nsec; + uint64_t input_clk_hz; + uint64_t timer_cycles; + + /* Stop timer and clear pending interrupts. */ + + am67_timer_stop(base_addr); + am67_timer_clear_overflow_int(base_addr); + + time_in_nsec = (uint64_t)params->period_in_nsec; + if (time_in_nsec == 0U) + { + time_in_nsec = params->period_in_usec * 1000U; + } + + input_clk_hz = params->input_clk_hz / params->input_pre_scaler; + timer_cycles = (input_clk_hz * time_in_nsec) / 1000000000U; + + /* If timerCycles > 32b then we cannot give accurate timing. */ + + /* Calculate count and reload value register value. */ + + count_val = 0xffffffffu - (uint32_t)timer_cycles - 1u; + + /* Keep reload value as 0, later if is auto-reload is enabled, + * it will be set a value > 0. + */ + + reload_val = 0; + + /* Calculate control register value, keep timer disabled. */ + + ctrl_val = 0; + if (params->input_pre_scaler > 1u) + { + uint32_t pre_scale_val; + + for (pre_scale_val = 8; pre_scale_val >= 1u; pre_scale_val--) + { + if ((params->input_pre_scaler & (0x1u << pre_scale_val)) != 0u) + { + break; + } + } + + /* Enable pre-scaler. */ + + ctrl_val |= (0x1u << 5); + + /* Set pre-scaler value. */ + + ctrl_val |= (((pre_scale_val - 1U) & 0x7u) << 2); + } + + if (params->oneshot_mode == 0u) + { + /* Auto-reload timer. */ + + ctrl_val |= (0x1u << 1); + reload_val = count_val; + } + + /* Set timer control value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TCLR); + *addr = ctrl_val; + + /* Set timer count value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TCRR); + *addr = count_val; + + /* Set reload value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TLDR); + *addr = reload_val; + + /* Enable/disable interrupts. */ + + if ((bool)params->enable_overflow_int == true) + { + /* Enable interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_INT_ENABLE); + *addr = (0x1u << TIMER_OVF_INT_SHIFT); + } + else + { + /* Disable interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_INT_DISABLE); + *addr = (0x1u << TIMER_OVF_INT_SHIFT); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_tick_isr + * + * Description: + * Timer tick interrupt service routine that clears the timer overflow + * interrupt and processes system timer events. + * + ****************************************************************************/ + +__attribute__((section(".tick_timer"))) +int timer_tick_isr(int irq, void *context, void *arg) +{ + am67_timer_clear_overflow_int(AM67_DMTIMER1_1MS_TIMER0_VADDR); + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * the architecture-specific timer was initialized). This function is + * functionally equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) Review Comment: Ditto for the remaining timer functions, make sure you adhere to the function specification. ########## arch/arm/src/am67/am67_mpuinit.h: ########## @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_mpuinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_AM67_MPUINIT_H +#define __ARCH_ARM_SRC_AM67_AM67_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <sys/types.h> + +#include "mpu.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_OF_REGION 5 + +#define ARM67_REGISTER_START_ADDR 0x0 +#define ARM67_TCMA_START_ADDR 0x0 +#define ARM67_TCMB_START_ADDR 0x41010000 +#define ARM67_MCU_MSRAM_START_ADDR 0x60000000 +#define ARM67_DDR_START_ADDR 0x80000000 + +#define ARM67_REGISTER_SIZE 2ul * 1024 * 1024 * 1024 +#define ARM67_TCMA_SIZE 32ul * 1024 +#define ARM67_TCMB_SIZE 32ul * 1024 +#define ARM67_MCU_MSRAM_SIZE 512ul * 1024 + +#define ARM67_DDR_SIZE 2ul * 1024 * 1024 * 1024 + +/* REGISTER_REGION + * Not Cacheable + * Not Bufferable + * Shareable + * Execute never + * P:RW U:R + */ +#define am67_register_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_S | \ + MPU_RACR_AP_RWRW) + +/* TCMA REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_tcma_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* TCMB REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_tcmb_region(base, size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_B | \ + MPU_RACR_C | \ + MPU_RACR_AP_RWRW) + +/* TCMB REGION + * Bufferable + * Cacheable + * P:RW U:R0 + * Allow user RW access, executable + */ +#define am67_mcu_msram_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/* DDR REGION + * Shareable + * Cacheable + * Bufferable + * P:RW U:RW + */ +#define am67_ddr_region(base,size) \ + mpu_configure_region(base, size, MPU_RACR_TEX(1) | \ + MPU_RACR_S | \ + MPU_RACR_C | \ + MPU_RACR_B | \ + MPU_RACR_AP_RWRW) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_mpu_disable_br + * + * Description: + * Disable the MPU background region by clearing bit 17 in the SCTLR + * register. + * + ****************************************************************************/ + +static inline void am67_mpu_disable_br(void) +{ + unsigned int sctlr = cp15_rdsctlr(); + sctlr &= ~(1 << 17); /* Clear bit 17 (disable background region) */ Review Comment: I would recommend that you give these special bits a name in your register mapping definition file, it makes the code much easier to read. Ex: ```c #define AM67_SCTLR_BG_REGION_EN (1 << 17) /* later in your function */ sctlr &= ~AM67_SCTLR_BG_REGION_EN; ``` Also, this would be a good place to use `modreg32` instead of the `cp15_wrsctlr`/`cp16_rdsctlr` functions. ########## arch/arm/src/am67/am67_irq.c: ########## @@ -0,0 +1,379 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <assert.h> + +#include "arm_internal.h" +#include "irq/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INTR_MAX_INTERRUPTS (512u) +#define INTR_MAX_PRIORITY (16u) +#define INTRC_BASE_ADDR 0x2fff0000u + +#define VIM_BIT_POS(j) ( (j) & 0x1fu ) +#define VIM_IRQVEC (0x18u) +#define VIM_ACTIRQ (0x20u) +#define VIM_RAW(j) (0x400u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_STS(j) (0x404u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_EN(j) (0x408u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_DIS(j) (0x40cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_MAP(j) (0x418u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_TYPE(j) (0x41cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_PRI(j) (0x1000u + ((j) * 0x4u)) +#define VIM_INT_VEC(j) (0x2000u + ((j) * 0x4u)) + +#define INTR_SUCCESS ((int32_t)0) +#define INTR_FAILURE ((int32_t)-1) +#define INTR_TIMEOUT ((int32_t)-2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num); +static void intr_ack_irq(uint32_t int_num); +static void intr_clear_irq(uint32_t int_num); +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority); +static uint32_t intr_get_irq_vec_addr(void); +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr); + +static void utils_data_and_instruction_barrier(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intr_get_irq + * + * Description: + * Return the interrupt status corresponding to the given int_num. + * + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num) +{ + volatile uint32_t *addr; Review Comment: Instead of modifying volatile pointers yourself, I would suggest using the `getreg32`/`putreg32` interfaces provided by NuttX. Keeps code consistent. Ditto for everywhere else you used this approach. ########## arch/arm/src/am67/am67_timer.c: ########## @@ -0,0 +1,494 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/timers/arch_alarm.h> +#include <fcntl.h> +#include <stdint.h> +#include <time.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TIMER0_CLOCK_SRC_MUX_ADDR (0x1081b0u) +#define TIMER0_CLOCK_SRC_HFOSC0_CLKOUT (0x0u) +#define TIMER0_BASE_ADDR (0x2400000u) + +#define AM67_DMTIMER1_1MS_TIMER0_VADDR 0x2400000 +#define AM67_DMTMR1MS_TIDR_OFFSET 0x0000 /* Identification Register Section */ +#define AM67_DMTMR1MS_TIOCP_CFG_OFFSET 0x0010 /* 1ms Timer OCP Configuration Register Section */ +#define AM67_DMTMR1MS_IRQ_EOI_OFFSET 0x0020 /* 1ms Timer IRQ Wakeup Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_RAW_OFFSET 0x0024 /* 1ms Timer IRQ Status Register */ +#define AM67_DMTMR1MS_IRQSTATUS_OFFSET 0x0028 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_SET_OFFSET 0x002c /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_CLR_OFFSET 0x0030 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQWAKEEN_OFFSET 0x0034 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_TCLR_OFFSET 0x0038 /* 1ms Timer Control Register */ +#define AM67_DMTMR1MS_TCRR_OFFSET 0x003c /* 1ms Timer Counter Register */ +#define AM67_DMTMR1MS_TLDR_OFFSET 0x0040 /* 1ms Timer Load Register */ +#define AM67_DMTMR1MS_TTGR_OFFSET 0x0044 /* 1ms Timer Trigger Register */ +#define AM67_DMTMR1MS_TWPS_OFFSET 0x0048 /* 1ms Timer Write Posting Bits Register */ +#define AM67_DMTMR1MS_TMAR_OFFSET 0x004c /* 1ms Timer Match Register */ +#define AM67_DMTMR1MS_TCAR1_OFFSET 0x0050 /* 1ms Timer Capture 1 Register */ +#define AM67_DMTMR1MS_TSICR_OFFSET 0x0054 /* 1ms Timer Synchronous Interface Control Register */ +#define AM67_DMTMR1MS_TCAR2_OFFSET 0x0058 /* 1ms Timer Capture 2 Register */ +#define AM67_DMTMR1MS_TPIR_OFFSET 0x005c /* 1ms Timer Positive Increment Register */ +#define AM67_DMTMR1MS_TNIR_OFFSET 0x0060 /* 1ms Timer Negative Increment Register */ +#define AM67_DMTMR1MS_TCVR_OFFSET 0x0064 /* 1ms Timer Counter Value Register */ +#define AM67_DMTMR1MS_TOCR_OFFSET 0x0068 /* 1ms Timer Overflow Counter Register */ +#define AM67_DMTMR1MS_TOWR_OFFSET 0x006c /* 1ms Timer Overflow Interrupts Register */ + +#define TIMER_OVF_INT_SHIFT (0x1) +#define TIMER_IRQ_EOI (0x20u) +#define TIMER_IRQ_STATUS_RAW (0x24u) +#define TIMER_IRQ_STATUS (0x28u) +#define TIMER_IRQ_INT_ENABLE (0x2cu) +#define TIMER_IRQ_INT_DISABLE (0x30u) +#define TIMER_TCLR (0x38u) +#define TIMER_TCRR (0x3cu) +#define TIMER_TLDR (0x40u) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct timer_params_s +{ + /* Input pre-scaler divisor ro apply + * + * Must be power of 2 and between 1 and 256 for GP Timer. + * + * This field is valid only when underlying timer is DM Timer. + * + * This field is not valid when underlying timer is RTI Timer, + * set to 1 in this case. + */ + + uint32_t input_pre_scaler; + + /* Timer input clock in unit of Hz before pre-scaler + * + * System initialization must make any system level muxes, PLLs, + * power required to input this clock are setup properly. + * + * Make sure this value is not 0. + */ + + uint32_t input_clk_hz; + + /* Timer period in units of usecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_usec; + + /* Timer period in units of nsecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_nsec; + + /* 0: continuous mode of operation + * 1: oneshot mode of operation + * + * Not supported for RTI timer, always set to 0 in this case. + */ + + uint32_t oneshot_mode; + + /* 0: do not enable timer overflow interrupt + * 1: enable timer overflow interrupt + */ + + uint32_t enable_overflow_int; + + /* 0: do not enable DMA trigger from timer + * 1: enable DMA trigger from timer + */ + + uint32_t enable_dma_trigger; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr); +static void am67_timer_stop(uint32_t base_addr); +static uint32_t am67_timer_get_count(uint32_t base_addr); +static void am67_timer_clear_overflow_int(uint32_t base_addr); +static void am67_timer_params_init(struct timer_params_s *params); +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ Review Comment: ditto ########## arch/arm/src/am67/am67_irq.c: ########## @@ -0,0 +1,379 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <assert.h> + +#include "arm_internal.h" +#include "irq/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INTR_MAX_INTERRUPTS (512u) +#define INTR_MAX_PRIORITY (16u) +#define INTRC_BASE_ADDR 0x2fff0000u + +#define VIM_BIT_POS(j) ( (j) & 0x1fu ) +#define VIM_IRQVEC (0x18u) +#define VIM_ACTIRQ (0x20u) +#define VIM_RAW(j) (0x400u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_STS(j) (0x404u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_EN(j) (0x408u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_DIS(j) (0x40cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_MAP(j) (0x418u + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_TYPE(j) (0x41cu + ((((j) >> 5) & 0xfu) * 0x20u)) +#define VIM_INT_PRI(j) (0x1000u + ((j) * 0x4u)) +#define VIM_INT_VEC(j) (0x2000u + ((j) * 0x4u)) + +#define INTR_SUCCESS ((int32_t)0) +#define INTR_FAILURE ((int32_t)-1) +#define INTR_TIMEOUT ((int32_t)-2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num); +static void intr_ack_irq(uint32_t int_num); +static void intr_clear_irq(uint32_t int_num); +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority); +static uint32_t intr_get_irq_vec_addr(void); +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr); + +static void utils_data_and_instruction_barrier(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intr_get_irq + * + * Description: + * Return the interrupt status corresponding to the given int_num. + * + ****************************************************************************/ + +static int32_t intr_get_irq(uint32_t *int_num) +{ + volatile uint32_t *addr; + int32_t status = INTR_FAILURE; + uint32_t value; + + *int_num = 0; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_ACTIRQ); + value = *addr; + + if ((value & 0x80000000u) != 0U) + { + *int_num = (value & (INTR_MAX_INTERRUPTS - 1U)); + status = INTR_SUCCESS; + } + + return status; +} + +/**************************************************************************** + * Name: intr_ack_irq + * + * Description: + * Acknowledge a specific interrupt number by writing to the interrupt + * controller's IRQVEC register. + * + ****************************************************************************/ + +static void intr_ack_irq(uint32_t int_num) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_IRQVEC); + *addr = int_num; +} + +/**************************************************************************** + * Name: intr_clear_irq + * + * Description: + * Clear a specific interrupt by setting the corresponding bit in the + * interrupt status register. + * + ****************************************************************************/ + +static void intr_clear_irq(uint32_t int_num) +{ + volatile uint32_t *addr; + uint32_t bit_pos; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_STS(int_num)); + bit_pos = VIM_BIT_POS(int_num); + + *addr = (0x1u << bit_pos); +} + +/**************************************************************************** + * Name: intr_set_irq_pri + * + * Description: + * Set the priority level (0–15) for a specified interrupt. + * + ****************************************************************************/ + +static void intr_set_irq_pri(uint32_t int_num, uint32_t priority) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_INT_PRI(int_num)); + + *addr = (priority & 0xfu); +} + +/**************************************************************************** + * Name: intr_get_irq_vec_addr + * + * Description: + * Get the interrupt vector address for a specific interrupt number from + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static uint32_t intr_get_irq_vec_addr(void) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_IRQVEC); + + return *addr; +} + +/**************************************************************************** + * Name: intr_set_irq_vec_addr + * + * Description: + * Set the interrupt vector address for a specific interrupt number into + * the corresponding interrupt controller register. + * + ****************************************************************************/ + +static void intr_set_irq_vec_addr(uint32_t int_num, uintptr_t vec_addr) +{ + volatile uint32_t *addr; + + addr = (volatile uint32_t *)(INTRC_BASE_ADDR + VIM_INT_VEC(int_num)); + + *addr = ((uint32_t)vec_addr & 0xfffffffcu); +} + +/**************************************************************************** + * Name: utils_data_and_instruction_barrier + * + * Description: + * Enforces CPU memory ordering by executing an Instruction Synchronization + * Barrier (ISB) followed by a Data Synchronization Barrier (DSB), + * ensuring all previous instructions complete and memory accesses are + * synchronized before continuing execution. + * + ****************************************************************************/ + +static void utils_data_and_instruction_barrier(void) +{ + __asm__ __volatile__( + " isb" + "\n\t" + : + : + : "memory"); + __asm__ __volatile__( + " dsb" + "\n\t" + : + : + : "memory"); +} + +/**************************************************************************** + * Public Functions Review Comment: This should be public function prototypes since they are only prototypes. ########## arch/arm/src/am67/chip.h: ########## @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/am67/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_AM67_CHIP_H +#define __ARCH_ARM_SRC_AM67_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: CSL_REG32_WR + * + * Description: + * Write a 32-bit value to a memory-mapped register using the raw write + * function with volatile pointer casting. + * + ****************************************************************************/ + +#define CSL_REG32_WR(p, v) (csl_reg32_wr_raw((volatile uint32_t *)(p), \ + (uint32_t)(v))) + +/**************************************************************************** + * Name: CSL_REG32_RD + * + * Description: + * Read a 32-bit value from a memory-mapped register using the raw read + * function with volatile pointer casting. + * + ****************************************************************************/ + +#define CSL_REG32_RD(p) (csl_reg32_rd_raw((volatile uint32_t *) (p))) + +#define CHIP_MPCORE_VBASE (0x0001800000) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: csl_reg32_wr_raw + * + * Description: + * Write a 32-bit value directly to a given memory-mapped + * register address. + * + ****************************************************************************/ + +static inline void csl_reg32_wr_raw(volatile uint32_t * const p, uint32_t v) Review Comment: These are re-implementations of `putreg32/getreg32` functions that exist on NuttX already, please use the existing functions instead. ########## boards/Kconfig: ########## @@ -1584,6 +1584,13 @@ config ARCH_BOARD_BEAGLEBONE_BLACK ---help--- This is the port of NuttX to the TI Beaglebone Black board. +config ARCH_BOARD_T3_GEM_O1 + bool "T3 Gemstone O1" + depends on ARCH_CHIP_AM67 + ---help--- + This is the port of NuttX to the T3 Gemstone O1 board. + See https://docs.t3gemstone.org/en/boards/o1/introduction for further information. Review Comment: Someone else can weigh in, but Kconfig should only link to NuttX docs imo. If you include this link on the NuttX doc page, that's fine, but all the necessary information for how to use the board port should exist on the NuttX docs and not externally. ########## arch/arm/src/am67/am67_timer.c: ########## @@ -0,0 +1,494 @@ +/**************************************************************************** + * arch/arm/src/am67/am67_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/arch.h> +#include <nuttx/spinlock.h> +#include <nuttx/timers/arch_alarm.h> +#include <fcntl.h> +#include <stdint.h> +#include <time.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TIMER0_CLOCK_SRC_MUX_ADDR (0x1081b0u) +#define TIMER0_CLOCK_SRC_HFOSC0_CLKOUT (0x0u) +#define TIMER0_BASE_ADDR (0x2400000u) + +#define AM67_DMTIMER1_1MS_TIMER0_VADDR 0x2400000 +#define AM67_DMTMR1MS_TIDR_OFFSET 0x0000 /* Identification Register Section */ +#define AM67_DMTMR1MS_TIOCP_CFG_OFFSET 0x0010 /* 1ms Timer OCP Configuration Register Section */ +#define AM67_DMTMR1MS_IRQ_EOI_OFFSET 0x0020 /* 1ms Timer IRQ Wakeup Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_RAW_OFFSET 0x0024 /* 1ms Timer IRQ Status Register */ +#define AM67_DMTMR1MS_IRQSTATUS_OFFSET 0x0028 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_SET_OFFSET 0x002c /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQSTATUS_CLR_OFFSET 0x0030 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_IRQWAKEEN_OFFSET 0x0034 /* 1ms Timer IRQ Enable Register */ +#define AM67_DMTMR1MS_TCLR_OFFSET 0x0038 /* 1ms Timer Control Register */ +#define AM67_DMTMR1MS_TCRR_OFFSET 0x003c /* 1ms Timer Counter Register */ +#define AM67_DMTMR1MS_TLDR_OFFSET 0x0040 /* 1ms Timer Load Register */ +#define AM67_DMTMR1MS_TTGR_OFFSET 0x0044 /* 1ms Timer Trigger Register */ +#define AM67_DMTMR1MS_TWPS_OFFSET 0x0048 /* 1ms Timer Write Posting Bits Register */ +#define AM67_DMTMR1MS_TMAR_OFFSET 0x004c /* 1ms Timer Match Register */ +#define AM67_DMTMR1MS_TCAR1_OFFSET 0x0050 /* 1ms Timer Capture 1 Register */ +#define AM67_DMTMR1MS_TSICR_OFFSET 0x0054 /* 1ms Timer Synchronous Interface Control Register */ +#define AM67_DMTMR1MS_TCAR2_OFFSET 0x0058 /* 1ms Timer Capture 2 Register */ +#define AM67_DMTMR1MS_TPIR_OFFSET 0x005c /* 1ms Timer Positive Increment Register */ +#define AM67_DMTMR1MS_TNIR_OFFSET 0x0060 /* 1ms Timer Negative Increment Register */ +#define AM67_DMTMR1MS_TCVR_OFFSET 0x0064 /* 1ms Timer Counter Value Register */ +#define AM67_DMTMR1MS_TOCR_OFFSET 0x0068 /* 1ms Timer Overflow Counter Register */ +#define AM67_DMTMR1MS_TOWR_OFFSET 0x006c /* 1ms Timer Overflow Interrupts Register */ + +#define TIMER_OVF_INT_SHIFT (0x1) +#define TIMER_IRQ_EOI (0x20u) +#define TIMER_IRQ_STATUS_RAW (0x24u) +#define TIMER_IRQ_STATUS (0x28u) +#define TIMER_IRQ_INT_ENABLE (0x2cu) +#define TIMER_IRQ_INT_DISABLE (0x30u) +#define TIMER_TCLR (0x38u) +#define TIMER_TCRR (0x3cu) +#define TIMER_TLDR (0x40u) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct timer_params_s +{ + /* Input pre-scaler divisor ro apply + * + * Must be power of 2 and between 1 and 256 for GP Timer. + * + * This field is valid only when underlying timer is DM Timer. + * + * This field is not valid when underlying timer is RTI Timer, + * set to 1 in this case. + */ + + uint32_t input_pre_scaler; + + /* Timer input clock in unit of Hz before pre-scaler + * + * System initialization must make any system level muxes, PLLs, + * power required to input this clock are setup properly. + * + * Make sure this value is not 0. + */ + + uint32_t input_clk_hz; + + /* Timer period in units of usecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_usec; + + /* Timer period in units of nsecs + * + * Internally timer_params_s.input_clk_hz and + * timer_params_s.input_pre_scaler is used to compute the value to be put + * inside the timer HW register. + * + * When value is 0, period_in_nsec is used instead. + * When both period_in_usec and period_in_nsec are non-zero, + * period_in_nsec is used. + */ + + uint32_t period_in_nsec; + + /* 0: continuous mode of operation + * 1: oneshot mode of operation + * + * Not supported for RTI timer, always set to 0 in this case. + */ + + uint32_t oneshot_mode; + + /* 0: do not enable timer overflow interrupt + * 1: enable timer overflow interrupt + */ + + uint32_t enable_overflow_int; + + /* 0: do not enable DMA trigger from timer + * 1: enable DMA trigger from timer + */ + + uint32_t enable_dma_trigger; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr); +static void am67_timer_stop(uint32_t base_addr); +static uint32_t am67_timer_get_count(uint32_t base_addr); +static void am67_timer_clear_overflow_int(uint32_t base_addr); +static void am67_timer_params_init(struct timer_params_s *params); +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: am67_timer_start + * + * Description: + * Start the timer by setting the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_start(uint32_t base_addr) +{ + volatile uint32_t *addr = (uint32_t *)(base_addr + TIMER_TCLR); + + *addr |= (0x1u << 0); +} + +/**************************************************************************** + * Name: am67_timer_stop + * + * Description: + * Stop the timer by clearing the enable bit in the timer control register. + * + ****************************************************************************/ + +static void am67_timer_stop(uint32_t base_addr) +{ + volatile uint32_t *addr = (volatile uint32_t *)(base_addr + TIMER_TCLR); + + *addr &= ~(0x1u << 0); +} + +/**************************************************************************** + * Name: am67_timer_get_count + * + * Description: + * Read and return the current timer count value from the timer counter + * register. + * + ****************************************************************************/ + +static uint32_t am67_timer_get_count(uint32_t base_addr) +{ + volatile uint32_t *addr = (volatile uint32_t *)(base_addr + TIMER_TCRR); + + return *addr; +} + +/**************************************************************************** + * Name: am67_timer_clear_overflow_int + * + * Description: + * Clear the timer overflow interrupt by writing to the interrupt status + * register and verify the interrupt is cleared. + * + ****************************************************************************/ + +static void am67_timer_clear_overflow_int(uint32_t base_addr) +{ + volatile uint32_t *addr; + uint32_t value = (0x1u << TIMER_OVF_INT_SHIFT); + + /* Clear status for overflow interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_STATUS); + *addr = value; + + /* Read back and make sure interrupt was indeed cleared, + * if not clear it again. + */ + + if ((bool)(*addr & value) == true) + { + *addr = value; + } +} + +/**************************************************************************** + * Name: am67_timer_params_init + * + * Description: + * Initialize timer parameters with default values including prescaler, + * clock frequency, period, and operational mode settings. + * + ****************************************************************************/ + +static void am67_timer_params_init(struct timer_params_s *params) +{ + params->input_pre_scaler = 1; + params->input_clk_hz = 25 * 1000000; + params->period_in_usec = 10000; + params->period_in_nsec = 0; + params->oneshot_mode = 0; + params->enable_overflow_int = 1; + params->enable_dma_trigger = 0; +} + +/**************************************************************************** + * Name: am67_timer_setup + * + * Description: + * Configure timer parameters including period, mode, prescaler, and + * interrupts based on the provided timer parameters structure. + * + ****************************************************************************/ + +static void am67_timer_setup(uint32_t base_addr, + struct timer_params_s *params) +{ + volatile uint32_t *addr; + uint32_t ctrl_val; + uint32_t count_val; + uint32_t reload_val; + uint64_t time_in_nsec; + uint64_t input_clk_hz; + uint64_t timer_cycles; + + /* Stop timer and clear pending interrupts. */ + + am67_timer_stop(base_addr); + am67_timer_clear_overflow_int(base_addr); + + time_in_nsec = (uint64_t)params->period_in_nsec; + if (time_in_nsec == 0U) + { + time_in_nsec = params->period_in_usec * 1000U; + } + + input_clk_hz = params->input_clk_hz / params->input_pre_scaler; + timer_cycles = (input_clk_hz * time_in_nsec) / 1000000000U; + + /* If timerCycles > 32b then we cannot give accurate timing. */ + + /* Calculate count and reload value register value. */ + + count_val = 0xffffffffu - (uint32_t)timer_cycles - 1u; + + /* Keep reload value as 0, later if is auto-reload is enabled, + * it will be set a value > 0. + */ + + reload_val = 0; + + /* Calculate control register value, keep timer disabled. */ + + ctrl_val = 0; + if (params->input_pre_scaler > 1u) + { + uint32_t pre_scale_val; + + for (pre_scale_val = 8; pre_scale_val >= 1u; pre_scale_val--) + { + if ((params->input_pre_scaler & (0x1u << pre_scale_val)) != 0u) + { + break; + } + } + + /* Enable pre-scaler. */ + + ctrl_val |= (0x1u << 5); + + /* Set pre-scaler value. */ + + ctrl_val |= (((pre_scale_val - 1U) & 0x7u) << 2); + } + + if (params->oneshot_mode == 0u) + { + /* Auto-reload timer. */ + + ctrl_val |= (0x1u << 1); + reload_val = count_val; + } + + /* Set timer control value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TCLR); + *addr = ctrl_val; + + /* Set timer count value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TCRR); + *addr = count_val; + + /* Set reload value. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_TLDR); + *addr = reload_val; + + /* Enable/disable interrupts. */ + + if ((bool)params->enable_overflow_int == true) + { + /* Enable interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_INT_ENABLE); + *addr = (0x1u << TIMER_OVF_INT_SHIFT); + } + else + { + /* Disable interrupt. */ + + addr = (volatile uint32_t *)(base_addr + TIMER_IRQ_INT_DISABLE); + *addr = (0x1u << TIMER_OVF_INT_SHIFT); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_tick_isr + * + * Description: + * Timer tick interrupt service routine that clears the timer overflow + * interrupt and processes system timer events. + * + ****************************************************************************/ + +__attribute__((section(".tick_timer"))) +int timer_tick_isr(int irq, void *context, void *arg) +{ + am67_timer_clear_overflow_int(AM67_DMTIMER1_1MS_TIMER0_VADDR); + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * the architecture-specific timer was initialized). This function is + * functionally equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) Review Comment: Not incredibly familiar with the `up_timer_*` functions, but I don't think your implementation matches the requirements at all? This function should return 0 on success, negated errno on failure. Your implementation returns the contents of some timer register. The timespec argument is unused, but it must contain the up-time you pull from the timer. I would also suggest adding a `DEBUGASSERT(ts != NULL)`. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. 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