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commit 2ce0c128f95ba8114f1cb5a63c8f407cff288865 Author: xiezhanpeng3 <[email protected]> AuthorDate: Thu Nov 13 13:59:32 2025 +0800 toolchain/ghs: Adapt .macro syntax for GHS compiler The GHS compiler uses different .macro syntax. Without this change, the GHS compiler reports error like: [asarm] (error #2014) nuttx/arch/arm/src/armv8-r/arm_vectors.S 155: expected a register vstmdb \ out ! , { s0 - s31 } ---------^ And: [asarm] (error #2179) nuttx/arch/arm/src/armv8-r/arm_vectors.S 141: unexpected token type (comma) encountered; expected type (char) .macro savefpu , out , tmp -----------------^ Co-authored-by: Chengdong Wang <[email protected]> Signed-off-by: xiezhanpeng3 <[email protected]> --- arch/arm/src/armv8-r/arm_vectors.S | 55 +++++++++++++++ arch/arm/src/armv8-r/cp15_cacheops.h | 131 +++++++++++++++++++++++++++++++++++ arch/arm/src/armv8-r/sctlr.h | 24 +++++++ 3 files changed, 210 insertions(+) diff --git a/arch/arm/src/armv8-r/arm_vectors.S b/arch/arm/src/armv8-r/arm_vectors.S index d4a6398ebd1..abe52d606c0 100644 --- a/arch/arm/src/armv8-r/arm_vectors.S +++ b/arch/arm/src/armv8-r/arm_vectors.S @@ -53,10 +53,16 @@ ****************************************************************************/ #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +#ifdef __ghs__ + .macro setirqstack tmp1 tmp2 + ldr sp, .Lirqstacktop /* SP = IRQ stack top */ + .endm +#else .macro setirqstack, tmp1, tmp2 ldr sp, .Lirqstacktop /* SP = IRQ stack top */ .endm #endif +#endif /**************************************************************************** * Name: setfiqstack @@ -68,10 +74,16 @@ ****************************************************************************/ #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +#ifdef __ghs__ + .macro setfiqstack tmp1 tmp2 + ldr sp, .Lfiqstacktop /* SP = FIQ stack top */ + .endm +#else .macro setfiqstack, tmp1, tmp2 ldr sp, .Lfiqstacktop /* SP = FIQ stack top */ .endm #endif +#endif /**************************************************************************** * Name: savefpu @@ -82,6 +94,26 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_FPU +#ifdef __ghs__ + .macro savefpu out tmp + /* Store all floating point registers. Registers are stored in numeric order, + * s0, s1, ... in increasing address order. + */ + + /* Store the floating point control and status register. */ + + vmrs tmp, fpscr /* Fetch the FPSCR */ + str tmp, [out, #-4]! /* Save the floating point control and status register */ + +#ifdef CONFIG_ARM_DPFPU32 + vstmdb.64 out!, {d16-d31} /* Save the full FP context */ + vstmdb.64 out!, {d0-d15} +#else + vstmdb out!, {s0-s31} /* Save the full FP context */ +#endif + + .endm +#else /* __ghs__ */ .macro savefpu, out, tmp /* Store all floating point registers. Registers are stored in numeric order, * s0, s1, ... in increasing address order. @@ -100,6 +132,7 @@ #endif .endm +#endif /* __ghs__ */ #endif /**************************************************************************** @@ -111,6 +144,27 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_FPU +#ifdef __ghs__ + .macro restorefpu in tmp + /* Load all floating point registers. Registers are loaded in numeric order, + * s0, s1, ... in increasing address order. + */ + +#ifdef CONFIG_ARM_DPFPU32 + vldmia.64 in!, {d0-d15} /* Restore the full FP context */ + vldmia.64 in!, {d16-d31} +#else + vldmia in!, {s0-s31} /* Restore the full FP context */ +#endif + + /* Load the floating point control and status register. At the end of the + * vstmia, \in will point to the FPSCR storage location. + */ + + ldr tmp, [in], #4 /* Fetch the floating point control and status register */ + vmsr fpscr, tmp /* Restore the FPSCR */ + .endm +#else .macro restorefpu, in, tmp /* Load all floating point registers. Registers are loaded in numeric order, * s0, s1, ... in increasing address order. @@ -130,6 +184,7 @@ ldr \tmp, [\in], #4 /* Fetch the floating point control and status register */ vmsr fpscr, \tmp /* Restore the FPSCR */ .endm +#endif /* __ghs__ */ #endif /**************************************************************************** diff --git a/arch/arm/src/armv8-r/cp15_cacheops.h b/arch/arm/src/armv8-r/cp15_cacheops.h index cadd8f85904..fa7c93d1be6 100644 --- a/arch/arm/src/armv8-r/cp15_cacheops.h +++ b/arch/arm/src/armv8-r/cp15_cacheops.h @@ -224,12 +224,21 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_enable_dcache tmp + mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */ + orr tmp, tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */ + isb +.endm +#else .macro cp15_enable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ isb .endm +#endif /**************************************************************************** * Name: cp15_disable_dcache @@ -245,12 +254,21 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_disable_dcache tmp + mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */ + bic tmp, tmp, #(0x1 << 2) /* Disable D cache */ + mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */ + isb +.endm +#else .macro cp15_disable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ isb .endm +#endif /**************************************************************************** * Name: cp15_enable_icache @@ -266,12 +284,21 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_enable_icache tmp + mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */ + orr tmp, tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */ + isb +.endm +#else .macro cp15_enable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ isb .endm +#endif /**************************************************************************** * Name: cp15_disable_icache @@ -287,12 +314,21 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_disable_icache tmp + mrc p15, 0, tmp, c1, c0, 0 /* Read SCTLR */ + bic tmp, tmp, #(0x1 << 12) /* Disable I cache */ + mcr p15, 0, tmp, c1, c0, 0 /* Update the SCTLR */ + isb +.endm +#else .macro cp15_disable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_icache_inner_sharable @@ -308,11 +344,19 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_icache_inner_sharable tmp + mov tmp, #0 + mrc p15, 0, tmp, c7, c1, 0 /* ICIALLUIS */ + isb +.endm +#else .macro cp15_invalidate_icache_inner_sharable, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_btb_inner_sharable @@ -328,11 +372,19 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_btb_inner_sharable tmp + mov tmp, #0 + mrc p15, 0, tmp, c7, c1, 6 /* BPIALLIS */ + isb +.endm +#else .macro cp15_invalidate_btb_inner_sharable, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_icache_all @@ -349,11 +401,19 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_icache_all tmp + mov tmp, #0 + mrc p15, 0, tmp, c7, c5, 0 /* ICIALLU */ + isb +.endm +#else .macro cp15_invalidate_icache_all, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_icache_bymva @@ -369,10 +429,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_icache_bymva va + mrc p15, 0, va, c7, c5, 1 /* ICIMVAU */ + isb +.endm +#else .macro cp15_invalidate_icache_bymva, va mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ isb .endm +#endif /**************************************************************************** * Name: cp15_flush_btb @@ -388,11 +455,19 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_flush_btb tmp + mov tmp, #0 + mrc p15, 0, tmp, c7, c5, 6 /* BPIALL */ + isb +.endm +#else .macro cp15_flush_btb, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ isb .endm +#endif /**************************************************************************** * Name: cp15_flush_btb_bymva @@ -408,10 +483,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_flush_btb_bymva va + mrc p15, 0, va, c7, c5, 7 /* BPIMVA */ + isb +.endm +#else .macro cp15_flush_btb_bymva, va mrc p15, 0, \va, c7, c5, 7 /* BPIMVA */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_dcacheline_bymva @@ -427,10 +509,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_dcacheline_bymva va + mrc p15, 0, va, c7, c6, 1 /* DCIMVAC */ + isb +.endm +#else .macro cp15_invalidate_dcacheline_bymva, va mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ isb .endm +#endif /**************************************************************************** * Name: cp15_invalidate_dcacheline_bysetway @@ -446,10 +535,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_invalidate_dcacheline_bysetway setway + mrc p15, 0, setway, c7, c6, 2 /* DCISW */ + isb +.endm +#else .macro cp15_invalidate_dcacheline_bysetway, setway mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ isb .endm +#endif /**************************************************************************** * Name: cp15_clean_dcache_bymva @@ -465,10 +561,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_clean_dcache_bymva va + mrc p15, 0, va, c7, c10, 1 /* DCCMVAC */ + isb +.endm +#else .macro cp15_clean_dcache_bymva, va mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ isb .endm +#endif /**************************************************************************** * Name: cp15_clean_dcache_bysetway @@ -484,10 +587,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_clean_dcache_bysetway setway + mrc p15, 0, setway, c7, c10, 2 /* DCCSW */ + isb +.endm +#else .macro cp15_clean_dcache_bysetway, setway mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ isb .endm +#endif /**************************************************************************** * Name: cp15_clean_ucache_bymva @@ -503,10 +613,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_clean_ucache_bymva va + mrc p15, 0, va, c7, c11, 1 /* DCCMVAU */ + isb +.endm +#else .macro cp15_clean_ucache_bymva, va mrc p15, 0, \va, c7, c11, 1 /* DCCMVAU */ isb .endm +#endif /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline_bymva @@ -522,10 +639,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_cleaninvalidate_dcacheline_bymva va + mrc p15, 0, va, c7, c14, 1 /* DCCIMVAC */ + isb +.endm +#else .macro cp15_cleaninvalidate_dcacheline_bymva, va mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ isb .endm +#endif /**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline @@ -541,10 +665,17 @@ * ****************************************************************************/ +#ifdef __ghs__ +.macro cp15_cleaninvalidate_dcacheline setway + mrc p15, 0, setway, c7, c14, 2 /* DCCISW */ + isb +.endm +#else .macro cp15_cleaninvalidate_dcacheline, setway mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ isb .endm +#endif #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv8-r/sctlr.h b/arch/arm/src/armv8-r/sctlr.h index 36a3239e7e6..f741d99a69a 100644 --- a/arch/arm/src/armv8-r/sctlr.h +++ b/arch/arm/src/armv8-r/sctlr.h @@ -496,6 +496,29 @@ /* Get the device ID */ +#ifdef __ghs__ +.macro cp15_rdid id + mrc p15, 0, id, c0, c0, 0 +.endm + +/* Read/write the system control register (SCTLR) */ + +.macro cp15_rdsctlr sctlr + mrc p15, 0, sctlr, c1, c0, 0 +.endm + +.macro cp15_wrsctlr sctlr + mcr p15, 0, sctlr, c1, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop +.endm +#else .macro cp15_rdid, id mrc p15, 0, \id, c0, c0, 0 .endm @@ -517,6 +540,7 @@ nop nop .endm +#endif #endif /* __ASSEMBLY__ */ /****************************************************************************
