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    from 1f5cd930a41 net/arp: support ARP entry learned on gratuitous ARP 
response
     add 72989778940 risc-v/litex: Add 64-bit S-mode vexiiriscv support for 
litex.

No new revisions were added by this update.

Summary of changes:
 arch/risc-v/Kconfig                                | 21 +++++++-
 arch/risc-v/src/litex/Make.defs                    |  2 +
 arch/risc-v/src/litex/hardware/litex_clint.h       |  4 +-
 arch/risc-v/src/litex/hardware/litex_memorymap.h   |  2 +-
 arch/risc-v/src/litex/hardware/litex_plic.h        |  2 +-
 arch/risc-v/src/litex/litex_irq.c                  |  8 +--
 arch/risc-v/src/litex/litex_irq_dispatch.c         |  2 +-
 .../configs/{nsh-tickless => nsh-vexii}/defconfig  |  8 ++-
 .../risc-v/litex/arty_a7/include/vexii_irq.h       | 40 +++++++--------
 .../risc-v/litex/arty_a7/include/vexii_memorymap.h | 59 ++++++++++------------
 boards/risc-v/litex/arty_a7/scripts/ld.script      |  2 +
 11 files changed, 83 insertions(+), 67 deletions(-)
 copy boards/risc-v/litex/arty_a7/configs/{nsh-tickless => nsh-vexii}/defconfig 
(85%)
 copy arch/risc-v/include/litex/irq.h => 
boards/risc-v/litex/arty_a7/include/vexii_irq.h (63%)
 copy libs/libc/builtin/lib_builtin_getname.c => 
boards/risc-v/litex/arty_a7/include/vexii_memorymap.h (54%)

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